OR2C04A datasheet(143/192 Pages) ETC

143 / 192 page

Data Sheet

June 1999

ORCA Series 2 FPGAs

Lucent Technologies Inc.

143

Timing Characteristics (continued)

Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.

Table 38A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write, Clocking Data into Latch/

Flip-Flop (MA/MB Modes)

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Parameter

Symbol

Speed

Unit

-2

-3

-4

-5

-6

-7

Min Max

Min Max Min Max Min Max Min Max Min Max

Setup Time (TJ = 85 °C, VDD = min):

Address to Clock (A[3:0], B[3:0] to CK)

Write Enable (WREN) to Clock (A4/B4 to CK)

Write-port Enable (WPE) to Clock (C0 to CK)

Data (WD[3:0] to CK)

MEM*_ASET

MEM*_WRSET

MEM*_PWRSET

MEM*_DSET

2.4

5.4

7.4

3.5

—

1.8

4.4

5.9

2.6

—

1.2

3.8

4.8

2.6

—

1.1

3.4

4.3

2.3

—

1.0

3.1

4.0

2.2

—

1.0

3.0

3.9

2.1

—

Hold Time (TJ = All, VDD = All): All

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

Clock to PFU Out (CK to Q[3:0])—Register

REG_DEL

—

2.4

—

2.0

—

1.9

—

1.5

—

1.3

—

1.0

Table 38B. OR2TxxB Asynchronous Memory Read During Write, Clocking Data into Latch/Flip-Flop

(MA/MB Modes)

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Parameter

Symbol

Speed

Unit

-7

-8

Min

Max

Min

Max

Setup Time (TJ = 85 °C, VDD = min):

Address to Clock (A[3:0], B[3:0] to CK)

Write Enable (WREN) to Clock (A4/B4 to CK)

Write-port Enable (WPE) to Clock (C0 to CK)

Data (WD[3:0] to CK)

MEM*_ASET

MEM*_WRSET

MEM*_PWRSET

MEM*_DSET

0.9

2.9

3.7

2.0

—

0.8

2.5

3.2

1.7

—

Hold Time (TJ = all, VDD = all): All

0.0

—

0.0

—

Clock to PFU Out (CK to Q[3:0])—Register

REG_DEL

—

1.0

—

1.0

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