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AD5697R

Data Sheet

Rev. 0 | Page 18 of 28

SERIAL INTERFACE

The AD5697R has a 2-wire I2C-compatible serial interface (refer

to I2

C-Bus Specification, Version 2.1, January 2000, available from

Philips Semiconductor). See Figure 2 for a timing diagram of a

typical write sequence. The AD5697R can be connected to an I2C

bus as a slave device, under the control of a master device. The

AD5697R can support standard (100 kHz) and fast (400 kHz) data

transfer modes. Support is not provided for 12-bit addressing

and general call addressing.

Input Shift Register

The input shift register of the AD5697R is 24 bits wide. Data is

loaded into the device as a 24-bit word under the control of

a serial clock input, SCL. The first eight MSBs make up the

command byte. The first four bits are the command bits (C3, C2,

C1, and C0) that control the mode of operation of the device

(see Table 7). The last four bits of the first byte are the address bits

(DAC B, 0, 0, and DAC A, see Table 8).

The data-word comprises 12-bit input code, followed by four don’t

care bits for the AD5697R. These data bits are transferred to the

input register on the 24 falling edges of SCL.

Commands can be executed on individual DAC channels or

both DAC channels, depending on the address bits selected.

Table 7. Command Definitions

Command

Description

No operation

Write to Input Register n (dependent

on LDAC)

Update DAC Register n with contents of

Input Register n

Write to and update DAC Channel n

Power down/power up DAC

Hardware LDAC mask register

Software reset (power-on reset)

Internal reference setup register

Reserved

…

Reserved

Table 8. Address Commands

Address (n)

DAC B

DAC A

Description

DAC A

DAC B

DAC A and DAC B

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to the dedicated input

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the contents

of the input registers selected and updates the DAC outputs

directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers and

update the DAC outputs directly.

Figure 43. Input Shift Register Content

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC B

DAC A

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

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