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STM32F407IG Datasheet(PDF) 106 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 106 Page - STMicroelectronics |
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106 / 167 page  Electrical characteristics STM32F405xx, STM32F407xx 106/167 Doc ID 022152 Rev 2 Table 50. I2C characteristics Symbol Parameter Standard mode I2C(1) 1. Guaranteed by design, not tested in production. Fast mode I2C(1)(2) 2. fPCLK1 must be at least 2 MHz to achieve standard mode I 2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - µs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. -0(4) 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - µs tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF |
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