STM32F407IG datasheet(108/167 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F405xx, STM32F407xx

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Doc ID 022152 Rev 2

I2S - SPI interface characteristics

Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S

are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 11.

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 52.

SPI characteristics(1)(2)

Remapped SPI1 characteristics to be determined.

TBD stands for “to be defined”.

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

37.5

MHz

Slave mode

37.5

tr(SCL)

tf(SCL)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

DuCy(SCK)

SPI slave input clock

duty cycle

Slave mode

tsu(NSS)

(3)

Based on characterization, not tested in production.

NSS setup time

Slave mode

4tPCLK

th(NSS)

(3)

NSS hold time

Slave mode

2tPCLK

tw(SCLH)

(3)

tw(SCLL)

(3)

SCK high and low time Master mode, fPCLK = TBD MHz

TBD

tsu(MI)

(3)

tsu(SI)

(3)

Data input setup time

Master mode

Slave mode

th(MI)

(3)

th(SI)

(3)

Data input hold time

Master mode

Slave mode

ta(SO)

(3)(4)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Data output access

time

Slave mode, fPCLK = 20 MHz

3 tPCLK

tdis(SO)

(3)(5)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Data output disable

time

Slave mode

tv(SO)

(3)(1)

Data output valid time

Slave mode (after enable edge)

tv(MO)

(3)(1)

Data output valid time

Master mode (after enable edge)

th(SO)

(3)

Data output hold time

Slave mode (after enable edge)

th(MO)

(3)

Master mode (after enable edge)

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