TPS51117RGYRG4 datasheet(17/31 Pages) TI

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Control

Logic

and

Driver

VFB

DRVL

VoltageDivider

PWM

VIN

DRVH

ESR

SwitchingModulator

0.75V

OutputCapacitor

ƒo +

ESR

ƒsw

R1 +

OUT *

0.75

TPS51117

www.ti.com...................................................................................................................................... SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009

APPLICATION INFORMATION

LOOP COMPENSATION AND EXTERNAL PARTS SELECTION

D-CAP™ Mode Operation

A buck converter system using D-CAP™ Mode can be simplified as shown in Figure 23.

Figure 23. Simplified Diagram of the Modulator

The VFB voltage is compared with the internal reference voltage after the divider resistors. The PWM comparator

determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep

the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output

voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.

For loop stability, the 0 dB frequency, f 0, defined in the follow equation must be lower than 1/4 of the switching

frequency.

(6)

As f 0 is determined solely by the output capacitor characteristics, loop stability of D-CAP™ Mode is determined

by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100

μF and ESR in range of 10 mΩ. These values make f 0 in the order of 100 kHz or less and the loop is stable.

However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode.

Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external component

configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient

feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is

approximately 15 mV at the comparing point. This generates Vripple = (VOUT/0.75) × 15 mV at the output node.

The output capacitor ESR should meet this requirement.

The external component selection is simple in D-CAP™ Mode:

1. Determine the value of R1 and R2

The recommended R2 value is 10 k

Ω to 100 kΩ. Calculate R1 by Equation 7.

(7)

2. Choose RTON

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