AD7829BN datasheet(13/28 Pages) AD

13 / 28 page

AD7822/AD7825/AD7829

Rev. C | Page 13 of 28

Capacitor C2 in Figure 15 is typically about 4 pF and can be

primarily attributed to pin capacitance. The resistor, R1, is a

lumped component made up of the on resistance of several

components, including that of the multiplexer and the track-

and-hold. This resistor is typically about 310 Ω. Capacitor C1

is the track-and-hold capacitor and has a capacitance of 0.5 pF.

Switch 1 is the track-and-hold switch, and Switch 2 is that of the

sampling capacitor, as shown in Figure 6 and Figure 7.

VIN

4pF

310Ω

SW1

0.5pF A

SW2

VDD

Figure 15. Equivalent Analog Input Circuit

When in track phase, Switch 1 is closed and Switch 2 is in

Position A. When in hold mode, Switch 1 opens and Switch 2

remains in Position A. The track-and-hold remains in hold

mode for 120 ns (see the Circuit Description section), after

which it returns to track mode and the ADC enters its conversion

phase. At this point, Switch 1 opens and Switch 2 moves to

Position B. At the end of the conversion, Switch 2 moves back

to Position A.

Analog Input Selection

On power-up, the default VIN selection is VIN1. When returning

to normal operation from power-down, the VIN selected is the

same one that was selected prior to initiation of power-down.

Table 6 shows the multiplexer address corresponding to each

analog input from VIN1 to VIN4(8) for the AD7825 or AD7829.

Table 6.

Analog Input Selected

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VIN8

Channel selection on the AD7825 and AD7829 is made without

the necessity of a write operation. The address of the next channel

to be converted is latched at the start of the current read operation,

that is, on the falling edge of RD while CS is low, as shown in

Figure 16. This allows for improved throughput rates in “channel

hopping” applications.

CONVST

DB0 TO DB7

A0 TO A2

EOC

t13

VALID

DATA

ADDRESS CHANNEL y

TRACK CHx

HOLD CHx

TRACK CHy

HOLD CHy

120ns

Figure 16. Channel Hopping Timing

There is a minimum time delay between the falling edge of RD

and the next falling edge of the CONVST signal, t13. This is the

minimum acquisition time required of the track-and-hold to

maintain 8-bit performance. Figure 17 shows the typical perform-

ance of the AD7825 when channel hopping for various acquisition

times. These results are obtained using an external reference

and internal VMID while channel hopping between VIN1 and VIN4

with 0 V on Channel 4 and 0.5 V on Channel 1.

ACQUISITION TIME (ns)

8.0

5.0

500

200

100

7.5

7.0

6.5

6.0

5.5

8.5

Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825

The on-chip track-and-hold can accommodate input frequencies

to 10 MHz, making the AD7822/AD7825/AD7829 ideal for

subsampling applications. When the AD7825 is converting a

10 MHz input signal at a sampling rate of 2 MSPS, the effective

number of bits typically remains above seven, corresponding to

a signal-to-noise ratio of 42 dBs, as shown in Figure 18.

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