AD7829BN datasheet(17/28 Pages) AD

17 / 28 page

AD7822/AD7825/AD7829

Rev. C | Page 17 of 28

PARALLEL INTERFACE

The parallel interface of the AD7822/AD7825/AD7829 is eight

bits wide. Figure 26 shows a timing diagram illustrating the

operational sequence of the AD7822/AD7825/AD7829 parallel

interface. The multiplexer address is latched into the AD7822/

AD7825/AD7829 on the falling edge of the RD input. The on-

chip track-and-hold goes into hold mode on the falling edge of

CONVST, and a conversion is also initiated at this point. When

the conversion is complete, the end of conversion line (EOC)

pulses low to indicate that new data is available in the output

logic low for a maximum time of 110 ns.

However, the EOC pulse can be reset high by a rising edge

of RD. This EOC line can be used to drive an edge-triggered

interrupt of a microprocessor. CS and RD going low accesses

the 8-bit conversion result. It is possible to tie CS permanently

low and use only RD to access the data. In systems where the

part is interfaced to a gate array or ASIC, this EOC pulse can be

applied to the CS and RD inputs to latch data out of the AD7822/

AD7825/AD7829 and into the gate array or ASIC. This means

that the gate array or ASIC does not need any conversion status

recognition logic, and it also eliminates the logic required in the

gate array or ASIC to generate the read signal for the AD7822/

AD7825/AD7829.

CONVST

EOC

DB0 TO DB7

A0 TO A2

t10

t11

t12

t13

VALID

DATA

CHANNEL

ADDRESS

Figure 26. AD7822/AD7825/AD7829 Parallel Port Timing

AD7829BN Datasheet(PDF) 17 Page - Analog Devices