HT56R656 datasheet(85/145 Pages) HOLTEK

85 / 145 page

Rev. 1.30

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Rev. 1.30

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HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

SI MC TL 2 Re gi st er

Tr ans mi t/R ec ei ve c om pl et e fl ag

1: f in is hed

0: i n pr og re ss

Wr it e co llis io n fl ag

1: c ol li si on

0: no co llis io n

SC S pi n e nabl e

1: enabl e

0: S CS fl oat in g

Da ta s hi ft o r der

1: M SB

0: L SB

SP I Cl o ck E dge Se le ct

1: s ee te xt

0: s ee te xt

SP I Cl o ck Po la ri ty

1: s ee te xt

0: s ee te xt

No t im pl em ent ed, r ead as " 0"

WC OL

TR F

CS EN

ML S

CK EG

CK PO L

SPI Control Register – SIMCTL2

SPI Communication

AftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,when

dataiswrittentotheSIMDRregister,transmission/receptionwillbeginsimultaneously.When

thedatatransferiscomplete,theTRFflagwillbesetautomatically,butmustbeclearedusingthe

applicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,

anydataintheSIMDRregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedinto

theSIMDRregister.ThemastershouldoutputanSCSsignaltoenabletheslavedevicebeforea

clocksignalisprovidedandslavedatatransfersshouldbeenabled/disabledbefore/afteranSCS

signalisreceived.

TheSPIwillcontinuetofunctionevenafteraHALTinstructionhasbeenexecuted.

SC K (C KP OL =1 , C KE G= 0)

SI ME N, C SE N= 1

SI ME N= 1, C SE N= 0 (E xt er nal P ul l- Hi gh)

SC K (C KP OL =0 , C KE G= 0)

SC K (C KP OL =1 , C KE G= 1)

SC K (C KP OL =0 , C KE G= 1)

SD O (C KE G= 0)

SD O (C KE G= 1)

SC S

SD I D at a C apt ur e

D 7/ D 0D 6/ D 1D 5/ D 2D 4/ D 3D 3/ D 4D 2/ D 5D 1/ D 6D 0/ D 7

Wr it e to S IM D R

SPI Master Mode Timing

HT56R656 Datasheet(PDF) 85 Page - Holtek Semiconductor Inc

HT56R656 Datasheet(HTML) 85 Page - Holtek Semiconductor Inc

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