ADS58C28IRGC datasheet(39/67 Pages) TI

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1.65

1.70

1.75

1.80

1.85

1.90

1.95

65.5

66.5

67.5

68.5

DRVDD Supply (V)

SNR

SFDR

Input Frequency = 150MHz

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

Differential Clock Amplitude (VPP)

SFDR

SNR

Input Frequency = 40MHz

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

Differential Clock Amplitude (VPP)

SFDR

SNR

Input Frequency = 150MHz

78.5

79.5

80.5

81.5

64.5

65.5

66.5

67.5

Input Clock Duty Cycle (%)

THD

SNR

Input Frequency = 10MHz

ADS58C28

www.ti.com

SBAS509B – JUNE 2010 – REVISED OCTOBER 2010

TYPICAL CHARACTERISTICS (continued)

All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP

differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High Perf Mode disabled, 0dB gain, DDR

LVDS output interface, and 32k point FFT, unless otherwise noted.

PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE

PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE

Figure 39.

Figure 40.

PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE

PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE

Figure 41.

Figure 42.

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