SBAS052 datasheet(7/17 Pages) TI1

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PCM1720

TYPICAL CONNECTION DIAGRAM

Figure 4 illustrates the typical connection diagram for

PCM1720 used in a stand-alone application.

SYSTEM CLOCK

The system clock for PCM1720 must be either 256fS or

384f

S, where fS is the audio sampling frequency (LRCIN),

typically 32kHz, 44.1kHz or 48kHz. The system clock is

used to operate the digital filter and the noise shaper. The

system clock input (SCKI) is at pin 2.

PCM1720 has a system clock detection circuit which auto-

matically detects the frequency, either 256fS or 384fS. The

system clock should be synchronized with LRCIN (pin 16),

but PCM1720 can compensate for phase differences. If the

phase difference between LRCIN and system clock is greater

than

±6 bit clocks (BCKIN), the synchronization is per-

formed automatically. The analog outputs are forced to a

bipolar zero state (VCC/2) during the synchronization func-

tion. Table I shows the typical system clock frequency

inputs for the PCM1720.

FIGURE 4. Typical Connection Diagram.

SAMPLING

SYSTEM CLOCK

RATE (LRCIN)

FREQUENCY (MHz)

256fS

384fS

32kHz

8.192

12.288

44.1kHz

11.2896

16.9340

48kHz

12.288

18.432

TABLE I. System Clock Frequencies vs Sampling Rate.

SPECIAL FUNCTIONS

PCM1720 includes several special functions, including digi-

tal attenuation, digital de-emphasis, soft mute, data format

selection and input word resolution. These functions are

controlled using a three-wire interface. MD (pin 6) is used

for the program data, MC (pin 5) is used to clock in the

program data, and ML (pin 4) is used to latch in the program

data. Table II lists the selectable special functions.

FUNCTION

DEFAULT MODE

Input Audio Data Format Selection

Normal Format

I2S Format

Input Audio Data Bit Selection

16/20/24 Bits

16 Bits

Input LRCIN Polarity Selection

Lch/Rch = High/Low

Lch/Rch = Low/High

De-emphasis Control

OFF

Soft Mute Control

OFF

Attenuation Control

0dB

Lch, Rch Individually

Lch, Rch Individually Fixed

Lch, Rch Common

Infinite Zero Detection Circuit Control

OFF

Operation Enable (OPE)

Enabled

Sample Rate Selection

Internal System Clock Selection

256fS

384fS

Sampling Frequency

44.1kHz Group

44.1kHz

48kHz Group

32kHz Group

Analog Output Mode

L, R, Mono, Mute

Stereo

TABLE II. Selectable Functions.

DIN

BCKIN

LRCIN

SCKI

RSTB

PCM

Audio Data

Processor

256f

S/384fS CLK

AGND

DGND

+5V Analog

OUTL

OUTR

ZERO

CAP

PCM1720

10µF

Post

LPF

Post

LPF

Analog

Mute

Analog

Mute

STRB

SCKO

SDO

PIO

System

Controller

Rch Analog Out

Lch Analog Out

200

Ω

Not Recommended For New Designs

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