AD9979BCPZ datasheet(22/56 Pages) AD

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AD9979

Rev. C | Page 22 of 56

HBLK, PBLK, and CLPOB Toggle Positions

The AD9979 uses an internal horizontal pixel counter to position

the HBLK, PBLK, and CLPOB toggle positions. The horizontal

counter does not reset to 0 until 12 CLI periods after the falling

edge of HD. This 12-cycle pipeline delay must be considered

when determining the register toggle positions. For example, if

CLPOBx_TOGy is 100 and the pipeline delay is not considered,

the final toggle position is applied at 112. To obtain the correct

toggle positions, the toggle position registers must be set to the

desired toggle position minus 12. For example, if the desired

toggle position is 100, CLPOBx_TOGy needs to be set to 88,

that is, 100 minus 12. Figure 53 shows the 12-cycle pipeline delay

referenced to the falling edge of HD.

Note that toggle positions cannot be programmed during the

12-cycle delay from the HD falling edge until the horizontal

counter has reset. See Figure 31 for an example of this restriction.

1HBLKTOGE1/HBLKTOGO1

(60 – 12) = 48

2HBLKTOGE2/HBLKTOGO2

100

(100 – 12) = 88

3CLPOBx_TOG1

103

(103 – 12) = 91

4CLPOBx_TOG2

112

(112 – 12) = 100

DESIRED

TOGGLE

POSITION

ACTUAL

VALUE

CLPOB

PIXEL NO.

112

103

100

Figure 30. Example of Register Setting to Obtain Desired Toggle Positions

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

NOTES

1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.

H-COUNTER

(PIXEL COUNTER)

N-1

N-2

N-3

N-4

N-5

N-6

N-7

N-8

N-9

N-10

N-11

N-12

H-COUNTER

RESET

Figure 31. Restriction for Toggle Position Placement

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