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LM5056 Datasheet(PDF) 9 Page - Texas Instruments |
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LM5056 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 46 page ![]() LM5056, LM5056A www.ti.com SNVS827A – OCTOBER 2012 – REVISED APRIL 2013 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. ADR1 19 I SMBUS address line 1. Tri-state address line. Should be connected to DGND, VDD, or left floating. ADR0 20 I SMBUS address line 0. Tri-state address line. Should be connected to DGND, VDD, or left floating. VDD input to internal digital circuitry. Provide a 5.0-V (±10% allowable) voltage supply to VDD to VDD 21 I power the internal digital circuitry. Connect a 1 μF capacitor on this pin to AGND for bypassing. Current range select pin. Connecting this pin to VDD or DGND selects between a full-scale current CL 22 O sense voltage range of 27.0 mV and 54.4 mV respectively. NC 23 - Bonded to die for testing purposes. Connect to the ground plane. NC 24 - Bonded to die for testing purposes. Connect to the ground plane. NC 25 - No connect. Not bonded to the die. Connect to the ground plane. NC 26 - No connect. Not bonded to the die. Connect to the ground plane. NC 27 - No connect. Not bonded to the die. Connect to the ground plane. NC 28 - No connect. Not bonded to the die. Connect to the ground plane. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM5056 LM5056A |
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