M68HC08 datasheet(126/332 Pages) FREESCALE

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Monitor ROM (MON)

Technical Data

MC68HC908JB16 — Rev. 1.1

126

Monitor ROM (MON)

Freescale Semiconductor

9.4.1 Entering Monitor Mode

Table 9-1 shows the pin conditions for entering monitor mode. As

specified in the table, monitor mode may be entered after a POR and will

allow communication at 19200 baud provided one of the following sets

of conditions is met:

1. If IRQ = VTST:

–

External clock on OSC1 is 12MHz

–

PTA3 = high

–

PTE3 = high

2. If $FFFE & $FFFF is blank (contains $FF):

–

External clock on OSC1 is 12MHz

–IRQ = VDD

–

PTE3 = high

Table 9-1. Mode Entry Requirements and Options

External Clock,

fXCLK

Bus

Frequency,

fBUS

Comments

VTST

(2)

12 MHz

(fXCLK)

High-voltage entry to

monitor mode.

38400 baud communication

on PTA0. COP disabled.

VTST

(2)

1101

12 MHz

6MHz

(fXCLK ÷ 2)

High-voltage entry to

monitor mode.

19200 baud communication

on PTA0. COP disabled.

VDD

BLANK

(contain

$FF)

XXX

12 MHz

6MHz

(fXCLK ÷ 2)

Low-voltage entry to

monitor mode.

19200 baud communication

on PTA0. COP disabled.

VDD

NOT

BLANK

XXXX

12 MHz

6MHz

(fXCLK ÷ 2)

Enters user mode.

If $FFFE and $FFFF is

blank, MCU will encounter

an illegal address reset.

Notes:

1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using VTST for monitor mode entry.

2. See Section 20. Electrical Specifications for VTST voltage level requirements.

Factory use only

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