M68HC08 datasheet(129/332 Pages) FREESCALE

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Monitor ROM (MON)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Monitor ROM (MON)

129

9.4.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. Transmit and receive baud rates must

be identical.

Figure 9-3. Monitor Data Format

9.4.3 Break Signal

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When

the monitor receives a break signal, it drives the PTA0 pin high for the

duration of two bits and then echoes back the break signal.

Figure 9-4. Break Transaction

9.4.4 Baud Rate

The communication baud rate is dependant on oscillator frequency,

fXCLK. The state of PTA3 also affects baud rate if entry to monitor mode

is by IRQ =VTST. When PTA3 is high, the divide by ratio is 625. If the

PTA3 pin is at logic zero upon entry into monitor mode, the divide by ratio

is 312.

BIT 5

START

BIT

BIT 0

BIT 1

STOP

BIT

START

BIT

BIT 2

BIT 3

BIT 4

BIT 6

BIT 7

MISSING STOP BIT

TWO-STOP-BIT DELAY BEFORE ZERO ECHO

Table 9-3. Monitor Baud Rate Selection

Monitor Mode

Entry By:

Oscillator Clock

Frequency,

fCLK

PTA3

Baud Rate

IRQ = VTST

12 MHz

38400 bps

12 MHz

19200 bps

Blank reset vector,

IRQ = VDD

12 MHz

19200 bps

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