M68HC08 datasheet(128/332 Pages) FREESCALE

128 / 332 page

Monitor ROM (MON)

Technical Data

MC68HC908JB16 — Rev. 1.1

128

Monitor ROM (MON)

Freescale Semiconductor

Figure 9-2. shows a simplified diagram of the monitor mode entry when

the reset vector is blank and IRQ = VDD. An external clock of 12MHz is

required for a baud rate of 19200.

Enter monitor mode with the pin configuration shown in Figure 9-1 by

pulling RST low and then high. The rising edge of RST latches monitor

mode. Once monitor mode is latched, the values on the specified pins

can change.

Once out of reset, the MCU waits for the host to send eight security

bytes. (See 9.5 Security.) After the security bytes, the MCU sends a

break signal (10 consecutive logic zeros) to the host, indicating that it is

ready to receive a command. The break signal also provides a timing

reference to allow the host to determine the necessary baud rate.

In monitor mode, the MCU uses different vectors for reset, SWI

(software interrupt), and break interrupt than those for user mode. The

alternate vectors are in the $FE page instead of the $FF page and allow

code execution from the internal monitor firmware instead of user code.

Table 9-2 is a summary of the vector differences between user mode

and monitor mode.

Table 9-2. Monitor Mode Vector Differences

Modes

Functions

COP

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

User

Enabled

$FFFE

$FFFF

$FFFC

$FFFD

$FFFC

$FFFD

Monitor

Disabled(1)

Notes:

1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts its

COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the

configuration register.

$FEFE

$FEFF

$FEFC

$FEFD

$FEFC

$FEFD

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