AD7854ARS datasheet(23/28 Pages) AD

23 / 28 page

AD7854/AD7854L

REV. B

–23–

PARALLEL INTERFACE

Reading

The timing diagram for a read cycle is shown in Figure 35. The

CONVST and BUSY signals are not shown here as the read

cycle may occur while a conversion is in progress or after the

conversion is complete.

The HBEN signal is low for the first read and high for the sec-

ond read. This ensures that it is the lower 12 bits of the 16-bit

word are output in the first read and the 8 MSBs of the 16-bit

word are output in the second read. If required, the HBEN

signal may be high for the first read and low for the second

read to ensure that the high byte is output in the first read

and the lower byte in the second read. The

CS and RD sig-

nals are gated together internally and level triggered active

low. Both

CS and RD may be tied together as the timing speci-

fication for t5 and t6 are both 0 ns min. The data is output a time t8

after both

CS and RD go low. The RD rising edge should be

used to latch the data by the user and after a time t9 the data

lines will go into their high impedance state.

In Figure 35, the first read outputs the 12 LSBs of the 16-bit

word on pins DB0 to DB11 (DB0 being the LSB of the 12-bit

read). The second read outputs the 8 MSBs of the 16-bit word

on pins DB0 to DB7 (DB0 being the LSB of the 8-bit read). If the

system has a 12-bit or a 16-bit data bus, only one read operation

is necessary to obtain the 12-bit conversion result (12 bits are

output in the first read). A second read operation is not required.

If the system has an 8-bit data bus then two reads are needed.

Pins DB0 to DB7 should be connected the 8-bit data bus. Pins

DB8 to DB11 should be tied to DGND or DVDD via 10 k

Ω

resistors. With this arrangement, HBEN is pulled low for the

first read and the 8 LSBs of the 16-bit word are output on pins

DB0 to DB7 (data on pins DB8 to DB11 will be ignored).

HBEN is pulled high for the second read and now the 8 MSBs

of the 16-bit word are output on pins DB0 to DB7.

DATA

VALID

t3 = 15ns MIN, t4 = 5ns MIN, t5 = t6 = 0ns MIN,

t8 = 50ns MAX, t9 = 5/40ns MIN/MAX, t10 = 70ns MIN

HBEN

DATA

t10

DATA

VALID

Figure 35. Read Cycle Timing Diagram Using

CS and RD

In the case where the AD7854/AD7854L is operated as a read-

only ADC, the

WR pin can be tied permanently high. The read

operation need only consist of one read if the system has a 12-

bit or a 16-bit data bus.

When both the

CS and RD signals are tied permanently low a

different timing arrangement results, as shown in Figure 36.

Here the data is output a time t20 before the falling edge of the

BUSY signal. This allows the falling edge of BUSY to be used

for latching the data. Again if HBEN is low during the conver-

sion the 12 LSBs of the 16-bit word will be output on pins DB0

to DB11. Bringing HBEN high causes the 8 MSBs of the 16-bit

word to be output on pins DB0 to DB7. Note that with this

arrangement the data lines are always active.

t1 = 100ns MIN, t20 = 70ns MIN,

t19 = t20 = 70ns MIN, t21 = t22 = 60ns MAX

tCONVERT

CONVERSION IS INITIATED ON THIS EDGE

t19

t20

t18

t21

t22

OLD DATA VALID

NEW DATA

VALID

(DB0–DB11)

NEW DATA

VALID

(DB8–DB11)

NEW DATA

VALID

(DB0–DB11)

NEW DATA

VALID

(DB8–DB11)

ON PINS DB0 TO DB11

ON PINS DB0 TO DB7

CONVST

BUSY

HBEN

DATA

Figure 36. Read Cycle Timing Diagram with

CS and RD

Tied Low

Writing

The timing diagram for a write cycle is shown in Figure 37. The

CONVST and BUSY signals are not shown here as the write

cycle may occur while a conversion is in progress or after the

conversion is complete.

To write a 16-bit word to the AD7854/AD7854L, two 8-bit

writes are required. The HBEN signal must be low for the first

write and high for the second write. This ensures that it is the

lower 8 bits of the 16-bit word are latched in the first write and

the 8 MSBs of the 16-bit word are latched in the second write.

For both write operations the 8 bits of data should be present on

pins DB0 to DB7 (DB0 being the LSB of the 8-bit write). Any

data on pins DB8 to DB11 is ignored when writing to the device.

The

CS and WR signals are gated together internally. Both CS

and

WR may be tied together as the timing specification for t

and t14 are both 0 ns min. The data is latched on the rising edge

WR. The data needs to be set up a time t

16 before the WR

rising edge and held for a time t17 after the WR rising edge.

DATA

VALID

t11

t12

t11

t12

t13

t14

t10

t15

t16

t17

HBEN

DATA

VALID

t11 = 0ns MIN, t12 = 5ns MIN, t13 = t14 = 0ns MIN,

t15 = 70ns MIN, t16 = 10ns MIN, t17 = 5ns MIN

Figure 37. Write Cycle Timing Diagram

Resetting the Parallel Interface

If random data has been inadvertently written to the test regis-

ter, it is necessary to write the 16-bit word 0100 0000 0000

0010 (in two 8-bit bytes) to restore the test register to its

default value.

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