AD7854ARS datasheet(25/28 Pages) AD

25 / 28 page

AD7854/AD7854L

REV. B

–25–

AD7854/AD7854L to DSP5600x

Figure 41 shows a parallel interface between the AD7854/

AD7854L and the DSP5600x series of DSPs. The AD7854/

AD7854L should be mapped into the top 64 locations of Y data

memory. If extra wait states are needed in this interface, they

can be programmed using the Port A bus control register (please

see DSP5600x User’s Manual for details). Data can be read

from the DSP5600x using the following instruction:

MOVE Y:ADCaddr, X 0

Data can be written to the AD7854/AD7854L using the follow-

ing two instructions:

MOVE X0, Y:ADCaddr

MOVE X1, Y:ADCaddr+1

Where ADCaddr is the address in the DSP5600x address space

to which the AD7854/AD7854L has been mapped.

DSP56000/

DSP56002*

A15–A1

IRQ

D23–D0

HBEN

BUSY

DB11–DB0

AD7854/

AD7854L*

ADDR

DECODE

ADDRESS BUS

DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 41. AD7854/AD7854L to DSP5600x Parallel Interface

AD7854/AD7854L to TMS320C30

Figure 40 shows a parallel interface between the AD7854/

AD7854L and the TMS320C3x family of DSPs. The

AD7854/AD7854L is interfaced to the Expansion Bus of the

TMS320C3x. Two wait states are required in this interface.

These can be programmed using the WTCNT bits of the

Expansion Bus Control register (see TMS320C3x Users Guide

for details). Data from the AD7854/AD7854L can be read

using the following instruction:

LDI *ARn,Rx

Data can be loaded into the AD7854/AD7854L using the

instructions:

STI Ry,*ARn++

STI Rz,*ARn--

where ARn is an auxiliary register containing the lower 16 bits

of the address of the AD7854/AD7854L in the TMS320C3x

memory space, Rx is the register into which the ADC data is

loaded during a load operation, Ry contains the 8 LSBs of

data and Rz contains the 8 MSBs of data to be written to the

AD7854/AD7854L.

TMS320C30*

XA12–XA1

XA0

IOSTRB

XR/

INTx

XD23–XD0

HBEN

BUSY

DB11–DB0

AD7854/

AD7854L*

ADDR

DECODE

EXPANSION ADDRESS BUS

EXPANSION DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 40. AD7854/AD7854L to TMS320C30 Parallel

Interface

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