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Data Sheet

AD7091

Rev. A | Page 17 of 20

SOFTWARE RESET

The AD7091 requires the user to initiate a software reset upon

power-up. Note that failure to apply the correct software reset

command may result in a device malfunction. The timing

diagram for the software reset operation is shown in Figure 28.

To issue a software reset,

1. Start a conversion by pulling CONVST low.

2. Read back the conversion result by pulling CS low after the

conversion is complete.

3. Between the second and eighth SCLK cycles, pull CS high

to short cycle the read operation.

4. At the end of the next conversion, the software reset is

executed.

As soon as a software reset is issued, the user can start another

conversion by pulling CONVST low.

INTERFACING WITH AN 8-/16-BIT SPI BUS

It is also possible to interface the AD7091 with a conventional

8-/16-bit SPI bus.

Performing conversions and reading results can be achieved by

configuring the host SPI interface for 16 bits, which results in

providing an additional four SCLK cycles to complete a conver-

sion compared with the standard interface methods (see the

Busy Indicator Enabled section and the Busy Indicator Disabled

section).

After the 13th SCLK falling edge with the busy indicator enabled

or after the 12th SCLK falling edge with the busy indicator disabled,

SDO returns to a high impedance state. The additional four bits

should be treated as don’t care bits by the host. All other timings

are as shown in Figure 26 and Figure 27, with tQUIET starting after

the 16th SCLK cycle.

A software reset can be performed by configuring the SPI bus for

eight bits and performing the operation described in the Software

Reset section.

CONVST

SHORT CYCLE READ

t10

SDO

EOC

EOC/

SOFTWARE

RESET

t12

NOTES

1. EOC IS THE END OF A CONVERSION.

SCLK

Figure 28. Software Reset Timing

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