Data Sheet

AD7798/AD7799

Rev. B | Page 15 of 28

Table 13. Operating Modes

MD2

MD1

MD0

Mode

0

0

0

Continuous-Conversion Mode (Default). In continuous-conversion mode, the ADC continuously performs conversions

and places the result in the data register. RDY goes low when a conversion is complete. After power-on, a channel

0

0

1

Single-Conversion Mode. When single-conversion mode is selected, the ADC powers up and performs a single

conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes

down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or

another conversion is performed.

0

1

0

Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are

still provided.

0

1

1

Power-Down Mode. In this mode, all AD7798/AD7799 circuitry is powered down, including the burnout currents.

1

0

0

Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration

takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the

calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is

placed in the offset register of the selected channel.

1

0

1

Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for

this calibration. When the gain equals 1, a calibration takes two conversion cycles to complete. For higher gains, four

conversion cycles are required to perform the full-scale calibration. RDY goes high when the calibration is initiated

and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The

measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale

calibrations cannot be performed when the gain equals 128. The ADC is factory-calibrated at a gain of 128 and this

factory-generated value is placed in the full-scale register on power up and when the gain is set to 128. With this

gain setting, a system full-scale calibration can be performed. To minimize the full-scale error, a full-scale calibration

is required each time the gain of a channel is changed.

1

1

0

System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins as

selected by the CH2 to CH0 bits. A system offset calibration takes two conversion cycles to complete. RDY goes high

when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode

following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A

zero-scale calibration is required each time the gain of a channel is changed.

1

1

1

System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins, as selected

by the CH2 to CH0 bits. A calibration takes two conversion cycles to complete. RDY goes high when the calibration

is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.

The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration

is required each time the gain of a channel is changed.

Table 14. Update Rates Available

FS3

FS2

FS1

FS0

Rejection @ 50 Hz/60 Hz

0

0

0

0

Reserved

0

0

0

1

470

4

0

0

1

0

242

8

0

0

1

1

123

16

0

1

0

0

62

32

0

1

0

1

50

40

0

1

1

0

39

48

0

1

1

1

33.2

60

1

0

0

0

19.6

101

90 dB (60 Hz only)

1

0

0

1

16.7

120

80 dB (50 Hz only)

1

0

1

0

16.7

120

65 dB

1

0

1

1

12.5

160

66 dB

1

1

0

0

10

200

69 dB

1

1

0

1

8.33

240

70 dB

1

1

1

0

6.25

320

72 dB

1

1

1

1

4.17

480

74 dB