AD5791 datasheet(4/28 Pages) AD

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AD5781

Data Sheet

Rev. D | Page 4 of 28

A, B Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Midscale Glitch Impulse

3.1

nV-sec

VREFP = +10 V, VREFN = −10 V

1.7

nV-sec

VREFP = +10 V, VREFN = 0 V

1.4

nV-sec

VREFP = +5 V, VREFN = 0 V

MSB Segment Glitch Impulse6

9.1

nV-sec

VREFP = +10 V, VREFN = −10 V, see Figure 42

3.6

nV-sec

VREFP = 10 V, VREFN = 0 V, see Figure 43

1.9

nV-sec

VREFP = 5 V, VREFN = 0 V, see Figure 44

Output Enabled Glitch Impulse

nV-sec

On removal of output ground clamp

Digital Feedthrough

0.4

nV-sec

DC Output Impedance (Normal Mode)

3.4

kΩ

DC Output Impedance (Output

Clamped to Ground)

kΩ

Spurious Free Dynamic Range

100

1 kHz tone, 10 kHz sample rate

Total Harmonic Distortion

1 kHz tone, 10 kHz sample rate

REFERENCE INPUTS3

VREFP Input Range

VDD − 2.5 V

VREFN Input Range

VSS + 2.5 V

DC Input Impedance

6.6

kΩ

VREFP, VREFN, code dependent,

typical at midscale code

Input Capacitance

VREFP, VREFN

LOGIC INPUTS3

Input Current8

−1

µA

Input Low Voltage, VIL

0.3 × IOVCC

IOVCC = 1.71 V to 5.5 V

Input High Voltage, VIH

0.7 × IOVCC

IOVCC = 1.71 V to 5.5 V

Pin Capacitance

LOGIC OUTPUT (SDO)3

Output Low Voltage, VOL

0.4

IOVCC = 1.71 V to 5.5 V, sinking 1 mA

Output High Voltage, VOH

IOVCC − 0.5 V

IOVCC = 1.71 V to 5.5 V, sourcing 1 mA

High Impedance Leakage Current

±1

µA

High Impedance Output Capacitance

POWER REQUIREMENTS

All digital inputs at DGND or IOVCC

VDD

7.5

VSS + 33

VSS

VDD − 33

−2.5

VCC

2.7

5.5

IOVCC

1.71

5.5

IOVCC ≤ VCC

IDD

4.2

5.2

ISS

4.9

ICC

600

900

µA

IOICC

140

µA

SDO disabled

DC Power Supply Rejection Ratio3, 9

±0.6

µV/V

VDD ± 10%, VSS = 15 V

±0.6

µV/V

VSS ± 10%, VDD = 15 V

AC Power Supply Rejection Ratio3

VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V

VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V

Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.

Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.

Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.

Valid for all voltage reference spans.

Guaranteed by design and characterization, not production tested.

The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,

lead capacitance, and so forth).

Includes noise contribution from AD8676BRZ voltage reference buffers.

Current flowing in an individual logic pin.

Includes PSRR of AD8676BRZ voltage reference buffers.

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