AD5791 datasheet(24/28 Pages) AD

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AD5781

Data Sheet

Rev. D | Page 24 of 28

AD5781 FEATURES

POWER-ON TO 0 V

The AD5781 contains a power-on reset circuit that, as well as

resetting all registers to their default values, controls the output

voltage during power-up. Upon power-on, the DAC is placed in

tristate (its reference inputs are disconnected), and its output is

clamped to AGND through a ~6 kΩ resistor. The DAC remains

in this state until programmed otherwise via the control

important to know the state of the DAC output while it is in the

process of powering up.

CONFIGURING THE AD5781

After power-on, the AD5781 must be configured to put it into

normal operating mode before programming the output. To do

this, the control register must be programmed. The DAC is

removed from tristate by clearing the DACTRI bit, and the

output clamp is removed by clearing the OPGND bit. At this

point, the output goes to VREFN unless an alternative value is first

programmed to the DAC register.

DAC OUTPUT STATE

The DAC output can be placed in one of three states, controlled

by the DACTRI and OPGND bits of the control register, as

shown in Table 16.

Table 16. AD5781 Output State Truth Table

DACTRI

OPGND

Output State

Normal operating mode.

Output is clamped via ~6 kΩ to AGND.

Output is in tristate.

Output is clamped via ~6 kΩ to AGND.

LINEARITY COMPENSATION

The integral nonlinearity (INL) of the AD5781 can vary

according to the applied reference voltage span; the LIN COMP

bits of the control register can be programmed to compensate

for this variation in INL. The specifications in this data sheet

are obtained with LIN COMP = 0000 for reference spans up to

and including 10 V and with LIN COMP = 1100 for a reference

span of 20 V. The default value of the LIN COMP bits is 0000.

OUTPUT AMPLIFIER CONFIGURATION

There are a number of different ways that an output amplifier

can be connected to the AD5781, depending on the voltage

references applied and the desired output voltage span.

Unity Gain Configuration

Figure 50 shows an output amplifier configured for unity gain,

in this configuration the output spans from VREFN to VREFP.

6.8kΩ 6.8kΩ

RFB

18-BIT

DAC

VREFPS

VREFPF

VREFP

VREFN

VREFNS

AD5781

1/2 AD8676

AD8675,

ADA4898-1,

ADA4004-1

1/2 AD8676

VREFNF

RFB

INV

VOUT

Figure 50. Output Amplifier in Unity Gain Configuration

A second unity gain configuration for the output amplifier is

one that removes an offset from the input bias currents of the

amplifier. It does this by inserting a resistance in the feedback

path of the amplifier that is equal to the output resistance of the

DAC. The DAC output resistance is 3.4 kΩ. By connecting R1

and RFB in parallel, a resistance equal to the DAC resistance is

available on-chip. Because the resistors are all on one piece of

silicon, they are temperature coefficient matched. To enable this

mode of operation, the RBUF bit of the control register must be set

to Logic 1. Figure 51 shows how the output amplifier is connected

to the AD5781. In this configuration, the output amplifier is in

unity gain and the output spans from VREFN to VREFP. This unity

gain configuration allows a capacitor to be placed in the

amplifier feedback path to improve dynamic performance.

18-BIT

DAC

VREFPS

10pF

VREFPF

VREFP

VREFN

VREFNS

AD5781

1/2 AD8676

AD8675,

ADA4898-1,

ADA4004-1

1/2 AD8676

VREFNF

VOUT

RFB

VOUT

INV

6.8kΩ

Figure 51. Output Amplifier in Unity Gain with Amplifier Input Bias Current

Compensation

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