AD822 datasheet(57/88 Pages) AD

57 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 57 of 88

8052 COMPATIBLE ON-CHIP PERIPHERALS

This section gives a brief overview of the various secondary

peripheral circuits that are also available to the user on-chip.

These remaining functions are mostly 8052 compatible (with a

few additional features) and are controlled via standard 8052

SFR bit definitions.

Parallel I/O

The ADuC841/ADuC842/ADuC843 use four input/output

ports to exchange data with external devices. In addition to

performing general-purpose I/O, some ports are capable of

external memory operations while others are multiplexed with

alternate functions for the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not be used

as a general-purpose I/O pin.

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port that is

directly controlled via the Port 0 SFR. Port 0 is also the

multiplexed low order address and data bus during accesses to

external program or data memory.

Figure 57 shows a typical bit latch and I/O buffer for a Port 0

port pin. The bit latch (one bit in the port’s SFR) is represented

as a Type D flip-flop, which clocks in a value from the internal

bus in response to a write to latch signal from the CPU. The Q

output of the flip-flop is placed on the internal bus in response

to a read latch signal from the CPU. The level of the port pin

itself is placed on the internal bus in response to a read pin

signal from the CPU. Some instructions that read a port activate

the read latch signal, and others activate the read pin signal. See

the Read-Modify-Write Instructions section for details.

CONTROL

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

DVDD

ADDR/DATA

P0.x

Figure 57. Port 0 Bit Latch and I/O Buffer

As shown in Figure 57, the output drivers of Port 0 pins are

switchable to an internal ADDR and ADDR/DATA bus by an

internal control signal for use in external memory accesses.

During external memory accesses, the P0 SFR has 1s written to

it, i.e., all of its bit latches become 1. When accessing external

memory, the control signal in Figure 57 goes high, enabling

push-pull operation of the output pin from the internal address

or data bus (ADDR/DATA line). Therefore, no external pull-ups

are required on Port 0 for it to access external memory.

In general-purpose I/O port mode, Port 0 pins that have 1s writ-

ten to them via the Port 0 SFR are configured as open-drain and

will therefore float. In this state, Port 0 pins can be used as high

impedance inputs. This is represented in Figure 57 by the NAND

gate whose output remains high as long as the control signal is

low, thereby disabling the top FET. External pull-up resistors are

therefore required when Port 0 pins are used as general-purpose

outputs. Port 0 pins with 0s written to them drive a logic low

output voltage (VOL) and are capable of sinking 1.6 mA.

Port 1

Port 1 is also an 8-bit port directly controlled via the P1 SFR.

Port 1 digital output capability is not supported on this device.

Port 1 pins can be configured as digital inputs or analog inputs.

By (power-on) default, these pins are configured as analog

inputs, i.e., 1 written in the corresponding Port 1 register bit. To

configure any of these pins as digital inputs, the user should

write a 0 to these port bits to configure the corresponding pin as

a high impedance digital input. These pins also have various

secondary functions as described in Table 25.

Table 25. Port 1 Alternate Pin Functions

Pin No.

Alternate Function

P1.0

T2 (Timer/Counter 2 External Input)

P1.1

T2EX (Timer/Counter 2 Capture/Reload Trigger)

P1.5

SS (Slave Select for the SPI Interface)

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

P1.x

TO ADC

Figure 58. Port 1 Bit Latch and I/O Buffer

Port 2

Port 2 is a bidirectional port with internal pull-up resistors

directly controlled via the P2 SFR. Port 2 also emits the high-

order address bytes during fetches from external program

memory, and middle and high order address bytes during

accesses to the 24-bit external data memory space.

As shown in Figure 59, the output drivers of Port 2 are switch-

able to an internal ADDR and ADDR/DATA bus by an internal

control signal for use in external memory accesses (as for

Port 0). In external memory addressing mode (CONTROL = 1),

the port pins feature push-pull operation controlled by the

internal address bus (ADDR line). However, unlike the P0 SFR

during external memory accesses, the P2 SFR remains unchanged.

AD822 Datasheet(PDF) 57 Page - Analog Devices

AD822 Datasheet(HTML) 57 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL