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EP3SE110 Datasheet(PDF) 102 Page - Altera Corporation |
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EP3SE110 Datasheet(HTML) 102 Page - Altera Corporation |
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102 / 341 page  1–92 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Table 1–59 and Table 1–60 list the EP3SL70 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1–59 lists the EP3SL70 column pin delay adders when using the regional clock. DIFFERENTIAL 1.8-V SSTL CLASS I 8mA GCLK t co 3.066 3.298 4.690 5.103 5.629 5.485 5.684 5.238 5.766 5.622 5.751 ns GCLK PLL t co 3.063 3.296 4.691 5.106 5.632 5.488 5.687 5.241 5.770 5.626 5.755 ns DIFFERENTIAL 1.8-V SSTL CLASS I 10mA GCLK t co 3.064 3.296 4.681 5.094 5.619 5.475 5.674 5.228 5.756 5.612 5.741 ns GCLK PLL t co 3.113 3.349 4.752 5.167 5.695 5.551 5.750 5.302 5.832 5.688 5.817 ns DIFFERENTIAL 1.8-V SSTL CLASS I 12mA GCLK t co 3.089 3.325 4.734 5.150 5.678 5.534 5.733 5.285 5.817 5.673 5.802 ns GCLK PLL t co 3.071 3.306 4.712 5.128 5.656 5.512 5.711 5.263 5.795 5.651 5.780 ns DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK t co 3.117 3.352 4.752 5.167 5.694 5.550 5.749 5.302 5.832 5.688 5.817 ns GCLK PLL t co 3.102 3.337 4.738 5.152 5.679 5.535 5.734 5.287 5.817 5.673 5.802 ns DIFFERENTIAL 1.8-V SSTL CLASS II 16mA GCLK t co 3.091 3.326 4.733 5.149 5.676 5.532 5.731 5.284 5.815 5.671 5.800 ns GCLK PLL t co 3.071 3.306 4.710 5.125 5.653 5.509 5.708 5.261 5.791 5.647 5.776 ns DIFFERENTIAL 2.5-V SSTL CLASS I 8mA GCLK t co 3.068 3.302 4.706 5.122 5.649 5.505 5.704 5.257 5.788 5.644 5.773 ns GCLK PLL tco 3.073 3.306 4.697 5.110 5.635 5.491 5.690 5.244 5.772 5.628 5.757 ns DIFFERENTIAL 2.5-V SSTL CLASS I 12mA GCLK t co 3.066 3.299 4.696 5.111 5.638 5.494 5.693 5.247 5.777 5.633 5.762 ns GCLK PLL tco 3.094 3.328 4.724 5.138 5.664 5.520 5.719 5.273 5.802 5.658 5.787 ns DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK t co 3.076 3.311 4.709 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 ns GCLK PLL t co 3.062 3.295 4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.618 5.747 ns Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–59. EP3SL70 Column Pin Delay Adders for Regional Clock Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V RCLK input adder 0.158 0.168 0.225 0.241 0.257 0.247 0.313 0.244 0.258 0.252 0.315 ns RCLK PLL input adder -0.014 -0.012 -0.007 -0.003 -0.002 -0.005 0.191 -0.003 -0.003 -0.004 0.191 ns RCLK output adder -0.114 -0.116 -0.137 -0.139 -0.141 -0.137 -0.215 -0.132 -0.133 -0.136 -0.215 ns RCLK PLL output adder 1.642 1.675 2.599 2.912 3.223 3.071 3.22 2.931 3.238 3.083 3.338 ns |
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