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EP3SE110 Datasheet(PDF) 105 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 105 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–95
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
1.8-V HSTL
CLASS II
GCLK
t
su
-0.846
-0.846
-1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417
-1.773
ns
t
h
0.984
0.984
1.431
1.562
1.707
1.639
1.993
1.562
1.707
1.639
1.993
ns
GCLK
PLL
t
su
-1.165
-1.105
-1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922
-2.263
ns
t
h
1.445
1.391
2.023
2.286
2.496
2.396
2.759
2.286
2.496
2.396
2.759
ns
1.5-V HSTL
CLASS I
GCLK
t
su
-0.846
-0.846
-1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417
-1.773
ns
t
h
0.984
0.984
1.431
1.562
1.707
1.639
1.993
1.562
1.707
1.639
1.993
ns
GCLK
PLL
t
su
-1.165
-1.105
-1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922
-2.263
ns
t
h
1.445
1.391
2.023
2.286
2.496
2.396
2.759
2.286
2.496
2.396
2.759
ns
1.5-V HSTL
CLASS II
GCLK
t
su
-0.835
-0.835
-1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398
-1.754
ns
t
h
0.973
0.973
1.421
1.551
1.688
1.620
1.974
1.551
1.688
1.620
1.974
ns
GCLK
PLL
t
su
-1.154
-1.094
-1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903
-2.244
ns
t
h
1.434
1.380
2.013
2.275
2.477
2.377
2.740
2.275
2.477
2.377
2.740
ns
1.2-V HSTL
CLASS I
GCLK
t
su
-0.835
-0.835
-1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398
-1.754
ns
t
h
0.973
0.973
1.421
1.551
1.688
1.620
1.974
1.551
1.688
1.620
1.974
ns
GCLK
PLL
t
su
-1.154
-1.094
-1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903
-2.244
ns
t
h
1.434
1.380
2.013
2.275
2.477
2.377
2.740
2.275
2.477
2.377
2.740
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.823
-0.823
-1.222 -1.328 -1.439 -1.382 -1.738 -1.328 -1.439 -1.382
-1.738
ns
t
h
0.961
0.961
1.411
1.540
1.672
1.604
1.958
1.540
1.672
1.604
1.958
ns
GCLK
PLL
t
su
-1.142
-1.082
-1.593 -1.813 -1.964 -1.887 -2.228 -1.813 -1.964 -1.887
-2.228
ns
t
h
1.422
1.368
2.003
2.264
2.461
2.361
2.724
2.264
2.461
2.361
2.724
ns
3.0-V PCI
GCLK
t
su
-0.823
-0.823
-1.222 -1.328 -1.439 -1.382 -1.738 -1.328 -1.439 -1.382
-1.738
ns
t
h
0.961
0.961
1.411
1.540
1.672
1.604
1.958
1.540
1.672
1.604
1.958
ns
GCLK
PLL
t
su
-1.142
-1.082
-1.593 -1.813 -1.964 -1.887 -2.228 -1.813 -1.964 -1.887
-2.228
ns
t
h
1.422
1.368
2.003
2.264
2.461
2.361
2.724
2.264
2.461
2.361
2.724
ns
3.0-V
PCI-X
GCLK
t
su
-0.928
-0.928
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626
-1.979
ns
t
h
1.064
1.064
1.523
1.669
1.917
1.849
2.204
1.669
1.917
1.849
2.204
ns
GCLK
PLL
t
su
-1.245
-1.187
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134
-2.469
ns
t
h
1.523
1.471
2.115
2.396
2.709
2.609
2.970
2.396
2.709
2.609
2.970
ns
Table 1–61. EP3SL110 Column Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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