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EP3SE110 Datasheet(PDF) 103 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 103 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–93
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–60 lists the EP3SL70 row pin delay adders when using the regional clock.
EP3SL110 I/O Timing Parameters
Table 1–61 through Table 1–65 list the maximum I/O timing parameters for EP3SL110
devices for single-ended I/O standards.
Table 1–61 lists the EP3SL110 column pins input timing parameters for single-ended
I/O standards.
Table 1–60. EP3SL70 Row Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.111
0.123
0.177
0.192
0.207
0.198
0.263
0.194
0.212
0.201
0.266
ns
RCLK PLL input adder
0.099
0.105
0.156
0.175
0.195
0.185
0.263
0.177
0.195
0.188
0.263
ns
RCLK output adder
-0.113
-0.127
-0.183 -0.198 -0.213 -0.205 -0.272 -0.202 -0.216
-0.21
-0.273
ns
RCLK PLL output adder
-0.107
-0.112
-0.164 -0.185 -0.202 -0.193 -0.258 -0.184 -0.204 -0.197 -0.257
ns
Table 1–61. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.917
-0.917
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627
-1.980
ns
t
h
1.053
1.053
1.524
1.667
1.918
1.850
2.205
1.667
1.918
1.850
2.205
ns
GCLK
PLL
t
su
-1.234
-1.176
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135
-2.470
ns
t
h
1.512
1.460
2.116
2.394
2.710
2.610
2.971
2.394
2.710
2.610
2.971
ns
3.3-V
LVCMOS
GCLK
t
su
-0.917
-0.917
-1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627
-1.980
ns
t
h
1.053
1.053
1.524
1.667
1.918
1.850
2.205
1.667
1.918
1.850
2.205
ns
GCLK
PLL
t
su
-1.234
-1.176
-1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135
-2.470
ns
t
h
1.512
1.460
2.116
2.394
2.710
2.610
2.971
2.394
2.710
2.610
2.971
ns
3.0-V LVTTL
GCLK
t
su
-0.928
-0.928
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626
-1.979
ns
t
h
1.064
1.064
1.523
1.669
1.917
1.849
2.204
1.669
1.917
1.849
2.204
ns
GCLK
PLL
t
su
-1.245
-1.187
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134
-2.469
ns
t
h
1.523
1.471
2.115
2.396
2.709
2.609
2.970
2.396
2.709
2.609
2.970
ns
3.0-V
LVCMOS
GCLK
t
su
-0.928
-0.928
-1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626
-1.979
ns
t
h
1.064
1.064
1.523
1.669
1.917
1.849
2.204
1.669
1.917
1.849
2.204
ns
GCLK
PLL
t
su
-1.245
-1.187
-1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134
-2.469
ns
t
h
1.523
1.471
2.115
2.396
2.709
2.609
2.970
2.396
2.709
2.609
2.970
ns
2.5 V
GCLK
t
su
-0.923
-0.923
-1.341 -1.466 -1.700 -1.645 -1.998 -1.466 -1.700 -1.645
-1.998
ns
t
h
1.059
1.059
1.532
1.681
1.936
1.868
2.223
1.681
1.936
1.868
2.223
ns
GCLK
PLL
t
su
-1.240
-1.182
-1.712 -1.954 -2.228 -2.153 -2.488 -1.954 -2.228 -2.153
-2.488
ns
t
h
1.518
1.466
2.124
2.408
2.728
2.628
2.989
2.408
2.728
2.628
2.989
ns



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