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EP3SE110 Datasheet(PDF) 132 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 132 Page - Altera Corporation

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1–122
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–72 lists the EP3SL150 row pins input timing parameters for single-ended I/O
standards.
Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.925
-0.964
-1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993
ns
t
h
1.040
1.094
1.544
1.677
1.910
1.851
2.173
1.698
1.917
1.860
2.212
ns
GCLK
PLL
t
su
0.988
1.009
1.642
1.858
1.971
1.855
1.796
1.865
1.993
1.875
1.848
ns
t
h
-0.737
-0.741
-1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363
ns
3.3-V
LVCMOS
GCLK
t
su
-0.925
-0.964
-1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993
ns
t
h
1.040
1.094
1.544
1.677
1.910
1.851
2.173
1.698
1.917
1.860
2.212
ns
GCLK
PLL
t
su
0.988
1.009
1.642
1.858
1.971
1.855
1.796
1.865
1.993
1.875
1.848
ns
t
h
-0.737
-0.741
-1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363
ns
3.0-V LVTTL
GCLK
t
su
-0.931
-0.975
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
ns
t
h
1.046
1.105
1.541
1.678
1.913
1.854
2.176
1.697
1.922
1.865
2.217
ns
GCLK
PLL
t
su
0.982
0.998
1.645
1.857
1.968
1.852
1.793
1.866
1.988
1.870
1.843
ns
t
h
-0.731
-0.730
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
ns
3.0-V
LVCMOS
GCLK
t
su
-0.931
-0.975
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
ns
t
h
1.046
1.105
1.541
1.678
1.913
1.854
2.176
1.697
1.922
1.865
2.217
ns
GCLK
PLL
t
su
0.982
0.998
1.645
1.857
1.968
1.852
1.793
1.866
1.988
1.870
1.843
ns
t
h
-0.731
-0.730
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
ns
2.5 V
GCLK
t
su
-0.919
-0.968
-1.366 -1.484 -1.700 -1.651 -1.972 -1.488 -1.694 -1.649 -2.008
ns
t
h
1.034
1.098
1.550
1.691
1.928
1.869
2.191
1.706
1.932
1.875
2.227
ns
GCLK
PLL
t
su
0.994
1.005
1.636
1.844
1.953
1.837
1.778
1.857
1.978
1.860
1.833
ns
t
h
-0.743
-0.737
-1.235 -1.393 -1.453 -1.365 -1.296 -1.399 -1.467 -1.378 -1.348
ns
1.8 V
GCLK
t
su
-0.949
-1.000
-1.406 -1.530 -1.590 -1.662 -1.875 -1.521 -1.582 -1.663 -1.913
ns
t
h
1.065
1.131
1.590
1.738
1.824
1.880
2.098
1.739
1.826
1.889
2.137
ns
GCLK
PLL
t
su
0.964
0.966
1.589
1.806
1.955
1.835
1.780
1.824
1.977
1.854
1.832
ns
t
h
-0.712
-0.698
-1.190 -1.356 -1.455 -1.362 -1.298 -1.366 -1.466 -1.372 -1.347
ns
1.5 V
GCLK
t
su
-0.939
-0.989
-1.382 -1.498 -1.522 -1.594 -1.807 -1.490 -1.517 -1.598 -1.848
ns
t
h
1.055
1.120
1.566
1.706
1.756
1.812
2.030
1.708
1.761
1.824
2.072
ns
GCLK
PLL
t
su
0.974
0.977
1.613
1.838
2.023
1.903
1.848
1.855
2.042
1.919
1.897
ns
t
h
-0.722
-0.709
-1.214 -1.388 -1.523 -1.430 -1.366 -1.397 -1.531 -1.437 -1.412
ns
1.2 V
GCLK
t
su
-0.879
-0.936
-1.303 -1.397 -1.363 -1.435 -1.648 -1.394 -1.362 -1.443 -1.693
ns
t
h
0.995
1.067
1.487
1.605
1.597
1.653
1.871
1.612
1.606
1.669
1.917
ns
GCLK
PLL
t
su
1.034
1.030
1.692
1.939
2.182
2.062
2.007
1.951
2.197
2.074
2.052
ns
t
h
-0.782
-0.762
-1.293 -1.489 -1.682 -1.589 -1.525 -1.493 -1.686 -1.592 -1.567
ns



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