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EP3SE110 Datasheet(PDF) 134 Page - Altera Corporation |
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EP3SE110 Datasheet(HTML) 134 Page - Altera Corporation |
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134 / 341 page  1–124 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Table 1–73 lists the EP3SL150 column pins output timing parameters for single-ended I/O standards. 1.2-V HSTL CLASS I GCLK t su -0.830 -0.877 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 ns t h 0.946 1.008 1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875 ns GCLK PLL t su 1.083 1.089 1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092 ns t h -0.831 -0.821 -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 ns 1.2-V HSTL CLASS II GCLK t su -0.830 -0.877 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 ns t h 0.946 1.008 1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875 ns GCLK PLL t su 1.083 1.089 1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092 ns t h -0.831 -0.821 -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 ns 3.0-V PCI GCLK t su -0.931 -0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns t h 1.046 1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns GCLK PLL t su 0.982 0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns t h -0.731 -0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns 3.0-V PCI-X GCLK t su -0.931 -0.975 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns t h 1.046 1.105 1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217 ns GCLK PLL t su 0.982 0.998 1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843 ns t h -0.731 -0.730 -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 ns Table 1–72. EP3SL150 Row Pins Input Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V 3.3-V LVTTL 4mA GCLK tco 3.422 3.439 4.768 5.127 5.625 5.473 5.808 5.127 5.625 5.473 5.808 ns GCLK PLL t co 3.898 3.841 5.355 5.880 6.341 6.161 6.543 5.880 6.341 6.161 6.543 ns 8mA GCLK tco 3.355 3.372 4.659 5.016 5.512 5.360 5.695 5.016 5.512 5.360 5.695 ns GCLK PLL t co 3.781 3.774 5.246 5.718 6.228 6.048 6.430 5.718 6.228 6.048 6.430 ns 12mA GCLK t co 3.269 3.286 4.555 4.918 5.420 5.268 5.603 4.918 5.420 5.268 5.603 ns GCLK PLL t co 3.692 3.688 5.142 5.583 6.136 5.956 6.338 5.583 6.136 5.956 6.338 ns 16mA GCLK t co 3.262 3.279 4.538 4.890 5.379 5.227 5.562 4.890 5.379 5.227 5.562 ns GCLK PLL t co 3.685 3.681 5.125 5.555 6.095 5.915 6.297 5.555 6.095 5.915 6.297 ns |
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