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EP3SE110 Datasheet(PDF) 135 Page - Altera Corporation |
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EP3SE110 Datasheet(HTML) 135 Page - Altera Corporation |
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135 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–125 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 3.3-V LVCMOS 4mA GCLK tco 3.428 3.445 4.772 5.132 5.632 5.480 5.815 5.132 5.632 5.480 5.815 ns GCLK PLL t co 3.901 3.847 5.359 5.892 6.348 6.168 6.550 5.892 6.348 6.168 6.550 ns 8mA GCLK tco 3.273 3.290 4.565 4.935 5.431 5.279 5.614 4.935 5.431 5.279 5.614 ns GCLK PLL t co 3.701 3.692 5.152 5.600 6.147 5.967 6.349 5.600 6.147 5.967 6.349 ns 12mA GCLK t co 3.280 3.297 4.559 4.914 5.405 5.253 5.588 4.914 5.405 5.253 5.588 ns GCLK PLL t co 3.703 3.699 5.146 5.579 6.121 5.941 6.323 5.579 6.121 5.941 6.323 ns 16mA GCLK t co 3.264 3.281 4.537 4.888 5.376 5.224 5.559 4.888 5.376 5.224 5.559 ns GCLK PLL t co 3.687 3.683 5.124 5.553 6.092 5.912 6.294 5.553 6.092 5.912 6.294 ns 3.0-V LVTTL 4mA GCLK t co 3.386 3.403 4.735 5.096 5.592 5.440 5.775 5.096 5.592 5.440 5.775 ns GCLK PLL t co 3.843 3.805 5.322 5.831 6.308 6.128 6.510 5.831 6.308 6.128 6.510 ns 8mA GCLK t co 3.275 3.292 4.605 4.962 5.455 5.303 5.637 4.962 5.455 5.303 5.637 ns GCLK PLL tco 3.713 3.694 5.192 5.659 6.170 5.991 6.371 5.659 6.170 5.991 6.371 ns 12mA GCLK t co 3.239 3.256 4.542 4.893 5.381 5.229 5.563 4.893 5.381 5.229 5.563 ns GCLK PLL tco 3.662 3.658 5.129 5.560 6.096 5.917 6.298 5.560 6.096 5.917 6.298 ns 16mA GCLK t co 3.221 3.238 4.513 4.865 5.352 5.200 5.535 4.865 5.352 5.200 5.535 ns GCLK PLL t co 3.644 3.640 5.100 5.530 6.070 5.888 6.270 5.530 6.070 5.888 6.270 ns 3.0-V LVCMOS 4mA GCLK t co 3.300 3.317 4.639 4.995 5.490 5.338 5.672 4.995 5.490 5.338 5.672 ns GCLK PLL t co 3.751 3.719 5.226 5.712 6.205 6.026 6.406 5.712 6.205 6.026 6.406 ns 8mA GCLK t co 3.221 3.238 4.515 4.866 5.355 5.203 5.537 4.866 5.355 5.203 5.537 ns GCLK PLL t co 3.644 3.640 5.102 5.531 6.083 5.891 6.271 5.531 6.083 5.891 6.271 ns 12mA GCLK t co 3.216 3.233 4.508 4.859 5.346 5.194 5.529 4.859 5.346 5.194 5.529 ns GCLK PLL t co 3.639 3.635 5.095 5.524 6.062 5.882 6.264 5.524 6.062 5.882 6.264 ns 16mA GCLK t co 3.207 3.224 4.494 4.844 5.331 5.179 5.514 4.844 5.331 5.179 5.514 ns GCLK PLL t co 3.630 3.626 5.081 5.509 6.057 5.867 6.249 5.509 6.057 5.867 6.249 ns Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 2 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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