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EP3SE110 Datasheet(PDF) 159 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 159 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–149
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–82 lists the EP3SL200 row pins input timing parameters for single-ended I/O
standards.
3.0-V
PCI-X
GCLK
t
su
-1.148
-1.184
-1.809 -1.777 -2.001 -1.933 -2.481
-1.777
-2.001
-1.933
-2.481
ns
t
h
1.296
1.330
2.031
2.010
2.258
2.176
2.723
2.010
2.258
2.176
2.723
ns
GCLK
PLL
t
su
-1.476
-1.476
-2.237 -2.273 -2.557 -2.476 -2.996
-2.273
-2.557
-2.476
-2.996
ns
t
h
1.789
1.789
2.726
2.778
3.112
2.999
3.542
2.778
3.112
2.999
3.542
ns
Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part 4 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–82. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V
LVTTL
GCLK
t
su
-1.298
-1.321
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
t
h
1.432
1.473
1.671
1.862
1.969
1.850
1.775
1.751
1.869
1.850
1.775
ns
GCLK
PLL
t
su
0.915
0.938
2.210
2.223
2.633
2.541
2.966
2.384
2.665
2.541
2.966
ns
t
h
-0.638
-0.643
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
3.3-V
LVCMOS
GCLK
t
su
-1.298
-1.321
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
t
h
1.432
1.473
1.671
1.862
1.969
1.850
1.775
1.751
1.869
1.850
1.775
ns
GCLK
PLL
t
su
0.915
0.938
2.210
2.223
2.633
2.541
2.966
2.384
2.665
2.541
2.966
ns
t
h
-0.638
-0.643
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
ns
3.0-V
LVTTL
GCLK
t
su
-1.304
-1.332
2.207
2.224
2.636
2.544
2.969
2.383
2.670
2.544
2.969
ns
t
h
1.438
1.484
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
ns
GCLK
PLL
t
su
0.909
0.927
1.674
1.861
1.966
1.847
1.772
1.752
1.864
1.847
1.772
ns
t
h
-0.632
-0.632
2.207
2.224
2.636
2.544
2.969
2.383
2.670
2.544
2.969
ns
3.0-V
LVCMOS
GCLK
t
su
-1.304
-1.332
2.216
2.237
2.651
2.559
2.984
2.392
2.680
2.559
2.984
ns
t
h
1.438
1.484
-1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730
ns
GCLK
PLL
t
su
0.909
0.927
1.665
1.848
1.951
1.832
1.757
1.743
1.854
1.832
1.757
ns
t
h
-0.632
-0.632
2.216
2.237
2.651
2.559
2.984
2.392
2.680
2.559
2.984
ns
2.5 V
GCLK
t
su
-1.292
-1.325
1.625
1.722
1.945
1.834
1.742
1.710
1.853
1.834
1.742
ns
t
h
1.426
1.477
2.254
2.297
2.649
2.557
2.982
2.425
2.681
2.557
2.982
ns
GCLK
PLL
t
su
0.921
0.934
-2.017 -2.051 -2.384 -2.307 -2.728 -2.173 -2.404 -2.307 -2.728
ns
t
h
-0.644
-0.639
1.625
1.722
1.945
1.834
1.742
1.710
1.853
1.834
1.742
ns
1.8 V
GCLK
t
su
-1.322
-1.354
1.649
1.754
2.013
1.902
1.810
1.741
1.918
1.902
1.810
ns
t
h
0.891
0.902
2.230
2.265
2.581
2.489
2.914
2.394
2.616
2.489
2.914
ns
GCLK
PLL
t
su
1.457
1.507
-1.993 -2.019 -2.316 -2.239 -2.660 -2.142 -2.339 -2.239 -2.660
ns
t
h
-1.312
-1.343
1.728
1.855
2.172
2.061
1.969
1.837
2.073
2.061
1.969
ns



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