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EP3SE110 Datasheet(PDF) 295 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 295 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–285
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–132 lists the EP3SE260 row pins input timing parameters for single-ended I/O
standards.
1.2-V HSTL
CLASS I
GCLK
t
su
-1.162
-1.106
-1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253
ns
t
h
1.310
1.254
1.940
2.027
2.204
2.052
2.490
2.027
2.204
2.052
2.490
ns
GCLK
PLL
t
su
-1.335
-1.385
-2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809
ns
t
h
1.652
1.700
2.622
2.581
2.880
2.767
3.350
2.581
2.880
2.767
3.350
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-1.150
-1.094
-1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237
ns
t
h
1.298
1.242
1.930
2.016
2.188
2.036
2.474
2.016
2.188
2.036
2.474
ns
GCLK
PLL
t
su
-1.323
-1.373
-2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793
ns
t
h
1.640
1.688
2.612
2.570
2.864
2.751
3.334
2.570
2.864
2.751
3.334
ns
3.0-V PCI
GCLK
t
su
-1.150
-1.094
-1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237
ns
t
h
1.298
1.242
1.930
2.016
2.188
2.036
2.474
2.016
2.188
2.036
2.474
ns
GCLK
PLL
t
su
-1.323
-1.373
-2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793
ns
t
h
1.640
1.688
2.612
2.570
2.864
2.751
3.334
2.570
2.864
2.751
3.334
ns
3.0-V
PCI-X
GCLK
t
su
-1.253
-1.197
-1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481
ns
t
h
1.399
1.343
2.044
2.148
2.436
2.284
2.723
2.148
2.436
2.284
2.723
ns
GCLK
PLL
t
su
-1.428
-1.476
-2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037
ns
t
h
1.743
1.789
2.726
2.699
3.112
2.999
3.583
2.699
3.112
2.999
3.583
ns
Table 1–131. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–132. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V
LVTTL
GCLK
t
su
-1.219
-1.374
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
ns
t
h
1.355
1.524
1.749
1.864
1.862
1.767
1.884
1.864
1.883
1.767
1.884
ns
GCLK
PLL
t
su
0.983
0.983
2.293
2.233
2.553
2.431
2.902
2.260
2.659
2.431
2.902
ns
t
h
-0.704
-0.685
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
ns
3.3-V
LVCMOS
GCLK
t
su
-1.219
-1.374
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
ns
t
h
1.355
1.524
1.749
1.864
1.862
1.767
1.884
1.864
1.883
1.767
1.884
ns
GCLK
PLL
t
su
0.983
0.983
2.293
2.233
2.553
2.431
2.902
2.260
2.659
2.431
2.902
ns
t
h
-0.704
-0.685
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646
ns
3.0-V
LVTTL
GCLK
t
su
-1.225
-1.385
2.290
2.234
2.556
2.434
2.905
2.259
2.664
2.434
2.905
ns
t
h
1.361
1.535
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646
ns
GCLK
PLL
t
su
0.977
0.972
1.752
1.863
1.859
1.764
1.881
1.865
1.878
1.764
1.881
ns
t
h
-0.698
-0.674
2.290
2.234
2.556
2.434
2.905
2.259
2.664
2.434
2.905
ns



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