LP55231 datasheet(30/53 Pages) TI

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LP55231

SNOSCR5 – MARCH 2013

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00 = no master fader set, clears master fader set for D1. Default setting.

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01 = MASTER FADER1 controls the D1 output.

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10 = MASTER FADER2 controls the D1 output.

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11 = MASTER FADER3 controls the D1 output.

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The duty cycle on D1 output will be D1 PWM register value (address 16H) multiplied with the value in the

MASTER FADER register.

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06 — Bit [5] LOG_EN

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0 = linear adjustment.

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1 = logarithmic adjustment.

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This bit is effective for both the program execution engine control and direct PWM control.

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06 — Bit [4:0] TEMP_COMP

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The reference temperature is +25°C (i.e. the temperature at which the compensation has no effect) and the

correction factor (slope) can be set in 0.1% 1/°C steps to any value between

−1.5% 1/°C and +1.5% 1/°C,

with a default to 0.0% 1/°C.

TEMP_COMP bits

Correction factor [%]

00000

Not activated - default setting after reset.

11111

−1.5 1/°C

11110

−1.4 1/°C

...

10001

−0.1 1/°C

10000

0 1/°C

00001

+0.1 1/°C

...

01110

+1.4 1/°C

01111

+1.5 1/°C

The PWM duty cycle at temperature T (in centigrade) can be obtained as follows: PWMF = [PWMS - (25 - T) *

correction factor * PWMS] / 2, where PWMF is the final duty cycle at temperature T, PWMS is the set PWM duty

cycle (PWM duty cycle is set in registers 16H to 1EH) and the value of the correction factor is obtained from the

table above.

For example, if the set PWM duty cycle in register 16H is 90%, temperature T is

−10°C and the chosen

correction factor is +1.5% 1/°C, the final duty-cycle PWMF for D1 output will be [90% - (25°C − (−10°C) ) * 1.5%

1/°C * 90%]/2 = [90% - 35 * 0.015 * 90%]/2 = 21.4%. Default setting 00000 means that the temperature

compensation is non-active and the PWM output (0 to 100%) is set solely by PWM registers D1 PWM to D9

PWM.

07 D2 CONTROL to 0E D9 CONTROL

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The control registers and control bits for D2 output to D9 output are similar to that given to D1, see the 06 –

Bit [5] and 06 – Bits [4:0] sections.

16 D1 PWM

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This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation

- direct PWM control is active after power up by default. Note: serial bus address auto increment is not

supported for register addresses from 16 to 1E.

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16 — Bits [7:0] PWM

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These bits set the D1 output PWM as shown in the figure below. Note: if the temperature compensation is

active, the maximum PWM duty cycle is 50% at +25°C. This is required to allow enough headroom for

temperature compensation over the temperature range

−30 °C to 90°C.

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