LP55231 datasheet(32/53 Pages) TI

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LP55231

SNOSCR5 – MARCH 2013

www.ti.com

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01 = forced to bypass mode (1x).

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10 = forced to 1.5x mode; output voltage is boosted to 4.5V.

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11 = automatic mode selection.

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36 — Bit [2] PWM_PS_EN

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Enables PWM powersave operation. Significant power savings can be achieved, for example, during ramp

instruction.

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36 — Bits [1:0] CLK_DET_EN and INT_CLK_EN

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Program execution is clocked with internal 32.7 kHz clock or with external clock. Clocking is controlled with

bits INT_CLK_EN and CLK_DET_EN in the following way:

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00 = forced external clock (CLK pin).

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01 = forced internal clock.

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10 = automatic selection.

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11 = internal clock.

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External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32.7 kHz

for correct operation. If a higher or a lower frequency is used, it will affect on the program execution engine

operation speed. The detector block does not limit the maximum frequency. External clock status can be

checked with read only bit EXT_CLK_USED in register address 3A, when the external clock detection is

enabled (Bit [1] CLK_DET_EN = high).

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If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on

this pin and extra current consumption.

37 ENGINE1 PC

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Program counter starting value for program execution engine 1; A value from 0000000 to 1011111. The

maximum value depends on program memory allocation between the three program execution engines.

38 ENGINE2 PC

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38 — Bits [6:0] PC

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Program counter starting value for program execution engine 2; A value from 0000000 to 1011111.

39 ENGINE3 PC

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39 — Bits [6:0] PC

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Program counter starting value for program execution engine 3; A value from 0000000 to 1011111.

3A STATUS/INTERRUPT

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3A — Bit [7] LEDTEST_MEAS_DONE

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This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register.

Typically the conversion takes 2.7 milliseconds to complete.

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1 = LED test done.

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0 = LED test not done.

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This bit is a read-only bit, and it is cleared (to “0”) automatically after a read operation.

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3A — Bit [6] MASK_BUSY

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Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.

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1 = Interrupt events will be masked i.e. no external interrupt will be generated from STARTUP_BUSY or

ENGINE_BUSY event (default).

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0 = External interrupt will be generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer

true. Reading the register 3A clears the status bits [5:4] and releases INT pin to high state.

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3A — Bit [5] STARTUP_BUSY

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A status bit which indicates that the device is running the internal startup sequence. See Modes of Operation

for details.

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1 = internal startup sequence running. Note: STARTUP_BUSY = 1 always when CHIP_EN bit is "0".

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0 = internal startup sequence completed.

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3A — Bit [4] ENGINE_BUSY

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A status bit which indicates that a program execution engine is clearing internal registers. Serial bus master

should not write or read program memory, or registers 00H, 37H to 39H or 4CH to 4EH, when this bit is set to

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