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LSM9DS0TR Datasheet(PDF) 69 Page - STMicroelectronics |
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LSM9DS0TR Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 74 page  DocID024763 Rev 2 69/74 LSM9DS0 Register description 74 8.63 TIME_LIMIT (3Bh) 8.64 TIME_LATENCY (3Ch) 8.65 TIME WINDOW (3Dh) 8.66 Act_THS (3Eh) Table 123. TIME_LIMIT register - TLI6 TLI5 TLI4 TLI3 TLI2 TLI1 TLI0 Table 124. TIME_LIMIT description TLI7-TLI0 Click time limit. Default value: 000 0000 Table 125. TIME_LATENCY register TLA7 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLA0 Table 126. TIME_LATENCY description TLA7-TLA0 Click time latency. Default value: 0000 0000 Table 127. TIME_WINDOW register TW7 TW6 TW5 TW4 TW3 TW2 TW1 TW0 Table 128. TIME_WINDOW description TW7-TW0 Click time window Table 129. TIME_WINDOW register -- Acth6 Acth5 Acth4 Acth3 Acth2 Acth1 Acth0 Table 130. TIME_WINDOW description Acth[6:0] Sleep-to-Wake, Return-to-Sleep activation threshold 1 LSb = 16 mg |
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