LSM9DS0TR datasheet(48/74 Pages) STMICROELECTRONICS

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LSM9DS0

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8.15

INT1_SRC_G (31h)

Interrupt source register. Read-only register.

Reading at this address clears the INT1_SRC IA bit (and eventually the interrupt signal on

the INT_G pin) and allows the refresh of data in the INT1_SRC register if the latched option

was chosen.

8.16

INT1_THS_XH_G (32h)

XHIE

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured value higher

than preset threshold)

XLIE

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured value lower

than preset threshold)

Table 44. INT1_CFG_G description (continued)

Table 45. INT1_SRC_G register

YHYL

XHXL

Table 46. INT1_SRC_G description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)

X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)

Table 47. INT1_THS_XH_G register

THSX14

THSX13

THSX12

THSX11

THSX10

THSX9

THSX8

Table 48. INT1_THS_XH_G description

THSX14 - THSX8

Interrupt threshold. Default value: 000 0000

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