LSM9DS0TR datasheet(29/74 Pages) STMICROELECTRONICS

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DocID024763 Rev 2

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LSM9DS0

Application hints

Figure 11. LSM9DS0 electrical connections

5.1

External capacitors

The C1 and C2 external capacitors should be low SR value, ceramic type construction (typ

recommended value 200 mOhm). Reservoir capacitor C1 is nominally 4.7 μF in

capacitance, with the set/reset capacitor C2 nominally 0.22 μF in capacitance.

The device core is supplied through the Vdd line. Power supply decoupling capacitors

(C4 = 100 nF ceramic, C3 = 10 μF Al) should be placed as near as possible to the supply

pin of the device (common design practice). All the voltage and ground supplies must be

present at the same time to have proper behavior of the IC (refer to Figure 11).

The functions of the device and the measured acceleration/magnetic field data are

selectable and accessible through the I2C / SPI interfaces.

The functions, the threshold and the timing of the three interrupt pins (INT_G, INT1_XM and

INT2_XM) can be completely programmed by the user through the I2C / SPI interfaces.

Pin 1 indicator

Res

TOP

VIEW

INT1_XM

Vdd

INT2_XM

Vdd_IO

C1= 4.7µF

C2=0.22µF

GND

C3= 10µF

GND

C4= 100nF

LSM9DS0TR Datasheet(PDF) 29 Page - STMicroelectronics