Sensors

26

Freescale Semiconductor

MMA7455L

CLR_INT1

1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A) depending on

Control1($18) INTREG[1:0] setting.

0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A)

CLR_INT2

1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A) depending on

Control1($18) INTREG[1:0] setting.

0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A).

00: INT1 Register is detecting Level while INT2 is detecting Pulse.

01: INT1 Register is detecting Pulse while INT2 is detecting Level.

time window and second time window > 0 then INT2 will detect the double pulse only.

INTPIN: INT1 pin is routed to INT1 bit in Detection Source Register ($0A) and INT2 pin is routed to INT2 bit in Detection Source

Register ($0A).

INTPIN: INT2 pin is routed to INT1 bit in Detection Source Register ($0A) and INT1 pin is routed to INT2 bit in Detection Source

Register ($0A).

XDA

1: X-axis is disabled for detection.

0: X-axis is enabled for detection.

YDA

1: Y-axis is disabled for detection.

0: Y-axis is enabled for detection.

ZDA

1: Z-axis is disabled for detection.

0: Z-axis is enabled for detection.

THOPT (This bit is valid for level detection only, not valid

for pulse detection)

0: Threshold value is absolute only

1: Integer value is available.

DFBW

0: Digital filter band width is 62.5 Hz

1: Digital filter band width is 125 Hz

LDPL

0: Level detection polarity is positive and detecting condition

is OR 3 axes.

1: Level detection polarity is negative detecting condition is

AND 3 axes.

PDPL

0: Pulse detection polarity is positive and detecting condition

is OR 3 axes.

1: Pulse detection polarity is negative and detecting condition

is AND 3 axes.

DRVO

0: Standard drive strength on SDA/SDO pin

1: Strong drive strength on SDA/SDO pin

$17: Interrupt Latch Reset (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

--

--

--

--

--

--

CLR_INT2

CLR_INT1

Function

0

0

0

0

0

0

0

0

Default

$18 Control 1 (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

DFBW

THOPT

ZDA

YDA

XDA

INTREG[1]

INTREG[0]

INTPIN

Function

000000

00

Default

Table 12. Configuring the Interrupt settings using Register $18 with INTREG[1:0] bits

INTREG[1:0]

“INT1” Register Bit

“INT2” Register Bit

00

Level detection

Pulse Detection

01

Pulse Detection

Level Detection

10

Single Pulse detection

Single or Double Pulse Detection

$19: Control 2 (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

DRVO

PDPL

LDPL

Function

0

0

0

0

0

0

0

0

Default