EVAL-AD1871EB datasheet(16/28 Pages) AD

16 / 28 page

AD1871

–16–

REV. 0

FUNCTIONAL DESCRIPTION

Clocking Scheme

The MCLK pin is the input for the master clock frequency to

the device. Nominally the MCLK frequency will be 256

¥ fS for

correct operation of the device. However, if the user’s MCLK is

a multiple of 256

¥ fS (perhaps 512 ¥ fS or 768 ¥ fS), it is possible

to divide down the MCLK frequency to a suitable internal master

clock frequency (IMCLK) using the MCLK divider block as

shown in Figure 8. The divide options can be chosen from pass-

through (/1), /2, or /3 corresponding with 256

¥ fS, 512 ¥ fS, or

768

¥ fS MCLKs, respectively. The MCLK divider can be con-

trolled using the MCD1–MCD0 Bits of Control Register III.

(see Table XIII.)

The resulting internal MCLK (IMCLK) is used to run the

decimating and filtering engine and must be chosen to be at a

ratio of 256

¥ fS.

SINC

FILTER

HALF-BAND

FILTERS

IMCLK

12.288MHz/

24.576MHz

6.144MHz

384kHz/

768kHz

48kHz/

96kHz

AMC BIT

(CONT REG I)

0/1

6.144MHz

ANALOG

INPUT

MCLK

DIVIDER

IMCLK

DIVIDER

48kHz/

96kHz

HPE BIT

(CONT REG I)

MODCLK

MODULATOR

HIGH-PASS

FILTERS

Figure 8. Clocking Scheme to Modulator and Filter Engine

Modulator

The AD1871’s analog

modulator section comprises a

second order multibit implementation using Analog Device’s

proprietary technology for best performance. As shown in

Figure 9, the two analog integrator blocks are followed by a

Flash ADC section that generates the multibit samples. The

output of the Flash ADC, which is thermometer encoded, is decoded

to binary for output to the filter sections and is scrambled for

feedback to the two integrator stages.

The modulator is optimized for operation at a sampling rate

of 6.144 MHz (which is 128

¥ fS at 48 kHz sampling and

¥ fS at 96 kHz sampling). The modulator clock control

(AMC Bit in Control Register I) is used to select the modulator

clock (MODCLK) as a ratio from the IMCLK. The modulator

clock divider options are /2 (default) for 48 kHz operation and

/4 for 96 kHz operation. When operating with an IMCLK of

12.288 MHz, the default divider setting (/2) gives a modulator clock

of 6.144 MHz. When operating with an IMCLK of 24.576 MHz,

the alternate divider setting (/4) gives a modulator clock of

6.144 MHz (see Figure 8).

If it is required to operate the device at a different output sample

rate than those detailed above, perhaps 44.1 kHz or 88.2 kHz,

the decimation filter cutoff characteristics can then be determined

from the normalized frequency response plot shown in TPC 6.

FLASH

ADC

SCRAMBLER

THERMO-

METER

BINARY

DECODER

FEEDBACK DACs

FROM

ANALOG

INPUT

SECTION

DIGITAL

OUTPUT

(4 BITS/6.144MHz)

Figure 9. Modulator Block Diagram

EVAL-AD1871EB Datasheet(PDF) 16 Page - Analog Devices

EVAL-AD1871EB Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL