EVAL-AD1871EB datasheet(23/28 Pages) AD

23 / 28 page

REV. 0

AD1871

–23–

Single-Ended Mode Enable

The Single-Ended Mode Enable Bits (SEL and SER for left and

right channels, respectively), when set to 1, are used to configure

single-ended input on VINxP and VINxN (input is selected by

state of MXL and MXR). In this mode, single-ended inputs taken

from either VINxP or VINxN (selected using the Mux Select

Bits—MXL and MXR) are internally converted to a differential

format to be applied to the modulator section (see Table XII).

Table XII. Differential/Single-Ended Select

SEL

SER

Input Setting

Left Channel Input

Æ Differential

Left Channel Input

Æ Single-Ended

Right Channel Input

Æ Differential

Right Channel Input

Æ Single-Ended

Master Clock Divider

The master clock divider allows the division of the external

MCLK frequency to a more suitable internal master clock

frequency (IMCLK). IMCLK must be 256

¥ fS; therefore, if

the available MCLK is not at 256

¥ fS but is a multiple of

this, the MCD allows conversion of MCLK to a suitable IMCLK

at 256

¥ fS (see Table XIII).

Table XIII. Master Clock Divider Settings

MCD1

MCD0

MCLK Division

IMCLK = MCLK (/1)

IMCLK = MCLK/2

IMCLK = MCLK/3

IMCLK = MCLK (/1)

Table IX. Control Register III (Address 0010b)

15–12

0010

MCD1

MCD0

SEL

SER

MEL

MXL

MER

MXR

9–8

Reserved

(Should Be Programmed to 0)

7–6

MCD1–MCD0 Master Clock Divider (See Table XIII)

SEL

Single-Ended Enable, Left Channel (0 = Differential (Default); 1 = Single-Ended)

SER

Single-Ended Enable, Right Channel (0 = Differential (Default); 1 = Single-Ended)

MEL

Mux/PGA Disable, Left Channel (0 = Enabled (Default); 1 = Disabled)

MXL

Mux Select, Left Channel (0 = VINLP Selected (Default); 1 = VINLN Selected)

MER

Mux/PGA Disable, Right Channel (0 = Enabled (Default); 1 = Disabled)

MXR

Mux Select, Right Channel (0 = VINRP Selected (Default); 1 = VINRN Selected)

Control Register III

Control Register III contains bit settings for configuration of the

analog input section (both left and right channels).

Mux Enable

The Mux Enable Left (MEL) and Mux Enable Right (MER)

are used to enable the analog buffers. When these bits are set to

1, the analog input buffers are powered down and input signals

must be applied directly to the modulator inputs via the CAPxP

and CAPxN pins. (see Figure 23). When MEL and MER are set

to 0 (default condition after reset), the analog input section is

enabled, (see Table X).

Table X. Mux Control Settings

MEL

MER

Input Setting

Left Channel Analog Buffer Enabled

Left Channel Analog Buffer Disabled

Right Channel Analog Buffer Enabled

Right Channel Analog Buffer Disabled

Mux Select

The Mux Select Bits (MXL and MXR for left and right channels,

respectively) are used to select the input from VINxP or VINxN

when the input is configured as single-ended. When MXx is set

to 0, the input is taken from VINxP. When MXx is set to 1, the

input is taken from VINxN, (see Table XI).

Table XI. Mux Select Settings

MXL

MXR

Input Setting

Left Channel Input from VINLP

Left Channel Input from VINLN

Right Channel Input from VINRP

Right Channel Input from VINRN

*Mux select settings are only valid when single-ended operation is enabled; SEL

and SER are set to 1.

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