DF1760P datasheet(8/17 Pages) TI1

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PCM1760P/U DF1760P/U

FUNCTIONS OF

THE DIGITAL FILTER

SYSTEM CLOCK

The DF1760 can accept a system clock of either 256fs or

384fs. If a 384fs system clock is used, the DF1760 divides

by 2/3 to create the 256fs system clock required for the

PCM1760. The system clock is applied to pin 15 (SYSCLK

input). The actual clock selection is done by setting pin 25

(CLKSEL input) “high” for 256fs clock and “LOW” for

384fs clock.

The detailed timing requirements for the system clock are

shown in Figure 3c.

CLKSEL

SYSCLK

256fs

384fs

MASTER/SLAVE MODE

The DF1760 can be used in both the master mode and slave

mode. In the master mode, the DF1760 outputs L/R (left/

right channel phase clock), SCLK (data clock) and FSYNC

(frame clock 2fs) signals. In the slave mode, the DF1760

accepts L/R, SCLK and FSYNC signals. The mode selection

is done by taking pin 24 (S/M INPUT) “HIGH” for slave

mode and “LOW” for master mode.

S/M

MODE

Slave

Master

OUTPUT DATA FORMAT

The serial output data has four possible formats. The selec-

tion of the formats can be done by the Mode 1 and Mode 2

inputs.

CALD

CALIBRATION

Disable

Enable

MODE 1

MODE 2

FORMATS

MSB First, 16 Bits, Falling Edge

MSB First, 20 Bits, Falling Edge

MSB First, 20 Bits, Rising Edge

LSB First, 20 Bits, Falling Edge

LRSC

L/R CLOCK AND CHANNEL

H = LCH,

L = RCH

L = LCH,

H = RCH

OVERFLOW DETECTION

When a near-to-clipping input condition is detected, OVL

output (Pin 1), or OVR output (Pin 2), becomes “HIGH” for

a duration of 4096/fs (about 85ms) depending upon on the

channel detected.

The OVL and OVR output return to “LOW” after

4096/fs duration automatically.

OFFSET CALIBRATION MODE

The offset error is calibrated by storing the digital data when

the input is zero in registers and subtracting it from the

future data with actual signal input.

To enable the calibration mode, set the CALD input (Pin 13)

“LOW”. The calibration mode is disabled by setting the

CALD input (Pin 13) “HIGH”. The calibration cycle is

initiated by setting the /PD input (Pin 21) “LOW” for more

than 2 system clock periods and then setting it “HIGH”.

During the calibration cycle, the CAL output (Pin 14)

becomes “HIGH”, all the serial data is forced to “LOW”,

and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19)

pins become input terminals after the completion of the

calibration cycle. The CAL output is “LOW”.

POWER DOWN MODE/RESET

The /PD input (Pin 21) has two functions. First, it should be

set at “HIGH” after application or restoration of power (V

and/or V

DD) to accomplish the power-on/mode reset func-

tion. The detail timing requirements for this function are

shown in Figure 3f. Second, the DF1760 is placed in the

power down mode by setting the /PD input (Pin 21) “LOW”.

Set the /PD input (Pin 21) “HIGH” for normal operation

mode.

LR CHANNEL PHASE CLOCK

The status of the LR channel phase clock can be set by the

LRSC input.

/PD

OPERATION

Normal

Power Down

DESCRIPTION

NAME

MIN

TYP

MAX

UNITS

Delay from Overflow Detection

to OVL (OVR) Output

––0

OVL (OVR) Output Pulse Width

–

4096

–

1/fs

FIGURE 3a. DF1760 Overflow Detection.

OVL (OVR)

–Detect Level

+Detect Level

The power dissipation of the DF1760 in the power down

mode is about 1/10 of the normal operation mode. During

the power down mode, the L/R, SCLK, and FSYNC pins

become input pins and all the serial data is forced “LOW”.

The 256fs output is enabled even in the power down mode.

The detailed timing of the power down mode operation and

the offset calibration is shown in Figure 3b.

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