®

PCM1760P/U DF1760P/U

12

ANALOG INPUT

CONDITION

DIGITAL OUTPUT

+2.55V

+Max Input

72000H

+2.50V to +2.55V

Overflow

+2.50V

+FSR

70000H

0V

BPZ (Ideal)

–2.50V

–FSR

90000H

–2.83V to –2.85V

Overflow

–2.85V

–Max Input

82000H

NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over

70000H or under 82FFFH of digital output code.

TABLE I. Output Codes.

POWER SUPPLY SEQUENCING

The PCM1760 requires

±V

avoid any possibility of latch-up, the

±V

applied first followed by –V

FIGURE 10. Illustration of Offset Calibration.

+fs

BPZ

–fs

0V

+fs

–fs

ANALOG INPUT

V

OS

+fs

BPZ

–fs

0V

+fs

–fs

ANALOG INPUT

Analog Input

V

OS

PCM1760

DF1760

CAL

PD

V

OS

POWER-ON RESET AND MODE RESET

The timing requirements for POWER-ON RESET and

MODE RESET are shown in Figure 3f. The DF1760 re-

quires POWER-ON RESET when power is applied or re-

stored. MODE RESET is required when any of the follow-

ing has been changed: system clock, master/slave mode,

output data format, L/R clock, calibration after POWER-ON

in slave mode.

This reset should be done by holding the /PD input (pin 21)

low for more than 2/fs. Suggested reset circuits are given in

Figures 11, 12 and 13.

CLOCK INPUT

After power is applied to the DF1760, the system clock

should be provided continuously. The DF1760 employs a

dynamic logic architecture.