LTC3548

14

3548fc

TYPICAL APPLICATIONS

RUN2

TO 5.5V

AT 400mA

AT 800mA

RUN1

POR

SW1

GND

SW2

MODE/SYNC

LTC3548

C1*

10μF

R5

100k

POWER-ON

RESET

C4, 33pF

C5, 68pF

L1

2.2μH

L2

4.7μH

R4

887k

R2

604k

R1

301k

R3

196k

C3

4.7μF

C2

10μF

3548 TA07

C1, C2: MURATA GRM219R60J106KE19

C3: MURATA GRM219R60J475KE19

L1: COILTRONICS LPO3310-222MX

L2: COILTRONICS LPO3310-472MX

*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,

ADDITIONAL CAPACITANCE MAY BE REQUIRED.

1mm Profile Core and I/O Supplies

Efficiency vs Load Current

LOAD CURRENT (mA)

1

100

95

90

85

80

75

70

65

60

10

100

1000

3548 TA08

3.3V

1.8V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

DD Package

10-Lead Plastic DFN (3mm

× 3mm)

(Reference LTC DWG # 05-08-1699 Rev B)

3.00 0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION

OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT

STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40

0.10

BOTTOM VIEW—EXPOSED PAD

1.65

0.10

(2 SIDES)

0.75 0.05

R = 0.125

TYP

2.38 0.10

(2 SIDES)

1

5

10

6

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV B 0309

0.25

0.05

2.38 0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 0.05

(2 SIDES)

2.15 0.05

0.50

BSC

0.70 0.05

3.55 0.05

PACKAGE

OUTLINE

0.25

0.05

0.50 BSC

PACKAGE DESCRIPTION