TLV2556

SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002

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PRINCIPLES OF OPERATION

data input—address/command bits

The four MSBs (D7–D4) of the input data register are the address or command. These bits can be used to

address one of the 11 input channels, select one of three reference-test voltages, activate the software

power-down mode, or access the second configuration register, CFGR2. All address/command bits affect the

current conversion, which is the conversion that immediately follows the current I/O cycle. They also allow

access to CFGR1 except for command 1111b, which allows access to CFGR2.

data output length

CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid

for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current

I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be

selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.

With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current

conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly

12 bits long for proper synchronization, even when this means corrupting the output data from a previous

conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.

With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication

with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial

data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must

be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the

previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current

I/O cycle.

With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit

serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream

during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even

when this means corrupting the output data from the previous conversion. The four LSBs of the conversion

result are truncated and discarded. The current conversion is started immediately after the eighth falling edge

of the current I/O cycle.

Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there

can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data

format is selected to be least significant bit first, since at the time the data length change becomes effective (six

rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,

when different data lengths are required within an application and the data length is changed between two

conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first

format.

LSB out first

D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion

result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first

always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to

another, the current I/O cycle is never disrupted.