www.ti.com

BCK

FSYNC

LRCK

DOUT

1.4 V

1.4 V

1.4 V

T0017-01

PCM1802

SLES023C – DECEMBER 2001 – REVISED JANUARY 2005

PARAMETER

MIN

TYP

MAX

UNIT

BCK period

150

ns

BCK pulse duration, high

60

ns

BCK pulse duration, low

60

ns

LRCK setup time to BCK rising edge

40

ns

LRCK hold time to BCK rising edge

20

ns

LRCK period

10

µs

FSYNC setup time to BCK rising edge

20

ns

FSYNC hold time to BCK rising edge

20

ns

Delay time, BCK falling edge to DOUT valid

–10

20

ns

Delay time, LRCK edge to DOUT valid

–10

20

ns

Rise time of all signals

10

ns

Fall time of all signals

10

ns

signal swing. Load capacitance of DOUT is 20 pF.

Figure 25. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)

17