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NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

T0020-05

Power Down, HPF Bypass, Oversampling Control

PCM1802

SLES023C – DECEMBER 2001 – REVISED JANUARY 2005

It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode,

data format, or oversampling control is changed.

Figure 28. ADC Digital Output for Loss of Synchronization and Resynchronization

PDWN (pin 7) controls the entire ADC operation. During power-down mode, both the supply current for the

analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized.

Also, DOUT (pin 12) is disabled and no system clock is accepted during power-down mode.

Power-Down Control

PDWN

MODE

LOW

Power-down mode

HIGH

Normal operation mode

The built-in function for dc component rejection can be bypassed using the BYPAS (pin 8) control. In bypass

mode, the dc components of the analog input signal, internal dc offset, etc., are also converted and included in

the digital output data.

HPF Bypass Control

BYPAS

HPF (HIGH-PASS FILTER) MODE

LOW

Normal (no dc component on DOUT) mode

HIGH

Bypass (dc component on DOUT) mode

OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator,

×64 or ×128. The ×128 mode is

system clock.

Oversampling Control

OSR

OVERSAMPLING RATIO

LOW

×64

HIGH

×128 (f

20