EP3C80 datasheet(136/274 Pages) ALTERA

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7–14

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

High-Speed I/O Standards Support

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Figure 7–11 shows the differential SSTL Class II interface.

Differential HSTL I/O Standard Support in the Cyclone III Device Family

The differential HSTL I/O standard is used for the applications designed to operate in

0V to 1.2 V, 0V to 1.5V, or 0V to 1.8V HSTL logic switching range. The CycloneIII

device family supports differential HSTL-18, HSTL-15, and HSTL-12 I/O standards.

The differential HSTL input standard is available on GCLK pins only, treating the

differential inputs as two single-ended HSTL and only decoding one of them. The

differential HSTL output standard is only supported at the PLL#_CLKOUT pins using

two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the

second output programmed to have opposite polarity.

The differential HSTL I/O standard requires two differential inputs with an external

reference voltage (VREF), as well as an external termination voltage (VTT) of 0.5 × VCCIO

to which termination resistors are connected.

f For more information about the differential HSTL signaling characteristics, refer to the

I/O Features in the Cyclone III Device Family, Cyclone III Device Data Sheet, and Cyclone III

LS Device Data Sheet chapters.

Figure 7–12 shows the differential HSTL Class I interface.

Figure 7–11. Differential SSTL Class II Interface

Note to Figure 7–11:

(1) PLL output clock pins do not support differential SSTL-18 Class II I/O standard.

Output Buffer

(1)

Receiver

VTT

Figure 7–12. Differential HSTL Class I Interface

Output Buffer

Receiver

Z0 = 50 Ω

VTT

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