EP3C80 datasheet(196/274 Pages) ALTERA

196 / 274 page

9–38

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Configuration Features

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

Figure 9–16 shows a multi-device PS configuration when both Cyclone III device

family is receiving the same configuration data.

PS Configuration Timing

A PS configuration must meet the setup and hold timing parameters and the

maximum clock frequency. When using a microprocessor or another intelligent host

to control the PS interface, ensure that you meet these timing requirements.

Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data

Notes to Figure 9–16:

(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the

chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.

(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same configuration

data into multiple devices.

(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],

refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.

(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot

equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.

External Host

(MAX II Device or

Microprocessor)

Memory

ADDR

Cyclone III Device Family

nSTATUS

CONF_DONE

nCE

nCEO

DATA[0]

GND

MSEL[3..0]

DATA[0] (4)

nCONFIG

DCLK (4)

nSTATUS

CONF_DONE

nCE

nCEO

MSEL[3..0]

N.C. (2)

DATA[0] (4)

nCONFIG

DCLK (4)

Cyclone III Device Family

N.C. (2)

GND

(3)

Buffers (4)

10 k



VCCIO (1) VCCIO (1)

10 k



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