 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EP3C80 Datasheet(PDF) 197 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
EP3C80 Datasheet(HTML) 197 Page - Altera Corporation |
|
|
197 / 274 page  Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family 9–39 Configuration Features August 2012 Altera Corporation Cyclone III Device Handbook Volume 1 Figure 9–17 shows the timing waveform for a PS configuration when using an external host device as an external host. Table 9–13 lists the PS configuration timing parameters for Cyclone III device family. Figure 9–17. PS Configuration Timing Waveform (1) Notes to Figure 9–17: (1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay. (3) After power-up, before and during configuration, CONF_DONE is low. (4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more convenient. When using the AS configuration scheme, DCLK is a Cyclone III device family output pin and must not be driven externally. (5) Do not leave the DATA[0] pin floating after configuration. Drive it high or low, whichever is more convenient. nCONFIG nSTATUS (2) CONF_DONE (3) DCLK DATA[0] User I/O INIT_DONE Bit 0 Bit 1 Bit 2 Bit 3 Bit n tCD2UM tCF2ST1 tCF2CD tCFG tCH tCL tDH tDSU tCF2CK tSTATUS tCLK tCF2ST0 tST2CK User Mode (5) Tri-stated with internal pull-up resistor (4) Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 1 of 2) Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 500 ns tCF2ST0 nCONFIG low to nSTATUS low — 500 ns tCFG nCONFIG low pulse width 500 — ns tSTATUS nSTATUS low pulse width 45 800 (1) s tCF2ST1 nCONFIG high to nSTATUS high — 800 (2) s tCF2CK nCONFIG high to first rising edge on DCLK 800 (1) — s tST2CK nSTATUS high to first rising edge of DCLK 2— s tDSU Data setup time before rising edge on DCLK 5— ns tDH Data hold time after rising edge on DCLK 0— ns tCH DCLK high time 3.2 — ns tCL DCLK low time 3.2 — ns tCLK DCLK period 7.5 — ns fMAX DCLK frequency — 100 (4) MHz tCD2UM CONF_DONE high to user mode (3) 300 650 s tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
