EP3C80 datasheet(198/274 Pages) ALTERA

198 / 274 page

9–40

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Configuration Features

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

PS Configuration Using a Download Cable

In this section, the generic term "download cable" includes the Altera USB-Blaster

universal serial bus (USB) port download cable, MasterBlaster™ serial/USB

communications cable, ByteBlaster II parallel port download cable, the

ByteBlasterMV™ parallel port download cable, and the Ethernet-Blaster

communications cable.

In the PS configuration with a download cable, an intelligent host (such as a PC)

transfers data from a storage device to the device using the download cable.

The programming hardware or download cable then places the configuration data

one bit at a time on the DATA[0] pin of the device. The configuration data is clocked

into the target device until CONF_DONE goes high. The CONF_DONE pin must have an

external 10-k pull-up resistor for the device to initialize.

When you use a download cable, setting the Auto-restart configuration after error

option does not affect the configuration cycle because you must manually restart

configuration in the Quartus II software when an error occurs. Additionally, the

Enable user-supplied start-up clock (CLKUSR)

option has no effect on the device

initialization because this option is disabled in the .sof when programming the device

using the Quartus II programmer and download cable. Therefore, if you turn on the

CLKUSR

option, you do not need to provide a clock on CLKUSR when you are

configuring the device with the Quartus II programmer and a download cable.

tCD2UMC

CONF_DONE

high to user mode with CLKUSR option on

tCD2CU + (initialization clock

cycles × CLKUSR period) (5)

——

Notes to Table 9–13:

(1) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

(2) This value is applicable if you do not delay configuration by externally holding nSTATUS low.

(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting the device.

(4) Cyclone III devices can support a DCLK fMAX of 133 MHz. Cyclone III LS devices can support a DCLK fMAX of 100 MHz.

(5) For more information about the initialization clock cycles required in Cyclone III device family, refer to Table 9–5 on page 9–10.

Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 2 of 2)

Symbol

Parameter

Minimum

Maximum

Unit

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