AD5313 datasheet(17/28 Pages) AD

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AD5303/AD5313/AD5323

Rev. B | Page 17 of 28

SERIAL INTERFACE

The AD5303/AD5313/AD5323 are controlled over a versatile,

3-wire serial interface, which operates at clock rates up to

30 MHz and is compatible with SPI, QSPI, MICROWIRE,

and DSP interface standards.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. Data is loaded into

the device as a 16-bit word under the control of a serial clock

input, SCLK. The timing diagram for this operation is shown in

Figure 5. The 16-bit word consists of four control bits followed

by 8 /10 /12 bits of DAC data, depending on the device type.

The first bit loaded is the MSB (Bit 15), which determines whether

the data is for DAC A or DAC B. Bit 14 determines the output

range (0 V to VREF or 0 V to 2 VREF). Bit 13 and Bit 12 control the

operating mode of the DAC.

Table 6. Control Bits

Bit

Name

Function

Power-On

Default

A/B

0: data written to DAC A

1: data written to DAC B

N/A

GAIN

0: output range of 0 V to VREF

1: output range of 0 V to 2 VREF

PD1

Mode bit

PD0

Mode bit

The remaining bits are DAC data bits, starting with the MSB

and ending with the LSB. The AD5323 uses all 12 bits of DAC

data; the AD5313 uses 10 bits and ignores the 2 LSBs. The

AD5303 uses eight bits and ignores the last four bits. The data

format is straight binary, with all 0s corresponding to 0 V output,

and all 1s corresponding to full-scale output (VREF − 1 LSB).

The SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can be transferred

into the device only while SYNC is low. To start the serial data

transfer, SYNC should be taken low, observing the minimum

SYNC to SCLK rising edge setup time, t4. After SYNC goes low,

serial data is shifted into the device’s input shift register on the

falling edges of SCLK for 16 clock pulses. Any data and clock

pulses after the 16th are ignored, and no further serial data

transfer occurs until SYNC is taken high and low again.

SYNC may be taken high after the falling edge of the 16th SCLK

pulse, observing the minimum SCLK falling edge to SYNC

rising edge time, t7.

After the end of serial data transfer, data is automatically

transferred from the input shift register to the input register

of the selected DAC. If SYNC is taken high before the 16th

falling edge of SCLK, the data transfer is aborted and the input

registers are not updated.

When data has been transferred into both input registers, the

DAC registers of both DACs may be simultaneously updated,

by taking LDAC low. CLR is an active low, asynchronous clear

that clears the input and DAC registers of both DACs to all 0s.

LOW POWER SERIAL INTERFACE

To reduce the power consumption of the device even further,

the interface only powers up fully when the device is being

written to. As soon as the 16-bit control word has been written

to the part, the SCLK and DIN input buffers are powered down.

They only power up again following a falling edge of SYNC.

DOUBLE-BUFFERED INTERFACE

The DACs all have double-buffered interfaces consisting of two

banks of registers—input registers and DAC registers. The input

digital code is transferred to the relevant input register on com-

pletion of a valid write sequence. The DAC register contains the

digital code used by the resistor string.

Access to the DAC register is controlled by the LDAC function.

When LDAC is high, the DAC register is latched and the input

DAC register. However, when LDAC is brought low, the DAC

ister are transferred to it.

This is useful if the user requires simultaneous updating of

both DAC outputs. The user may write to both input registers

individually and then, by pulsing the LDAC input low, both

outputs update simultaneously.

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that LDAC was brought low. Normally, when LDAC

is brought low, the DAC registers are filled with the contents of

the input registers. In the case of the AD5303/AD5313/AD5323,

the part only updates the DAC register if the input register has

been changed since the last time the DAC register was updated,

thereby removing unnecessary digital crosstalk.

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