DM163006 datasheet(232/320 Pages) MICROCHIP

232 / 320 page

PIC18C601/801

DS39541A-page 232

Advance Information

 2001 Microchip Technology Inc.

COMF

Complement f

Syntax:

[ label ] COMF

f [,d [,a]]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

→ dest

Status Affected:

N,Z

Encoding:

0001

11da

ffff

Description:

The contents of register ’f’ are com-

plemented. If ’d’ is 0 the result is

stored in WREG. If ’d’ is 1 the result

is stored back in register ’f’

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, the Bank

will be selected as per the BSR

value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

COMF

REG

Before Instruction

REG

13h

After Instruction

REG

13h

WREG

0ECh

(f )

CPFSEQ

Compare f with WREG,

skip if f = WREG

Syntax:

[ label ] CPFSEQ

f [,a]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) – (WREG),

skip if (f) = (WREG)

(unsigned comparison)

Status Affected:

None

Encoding:

0110

001a

ffff

Description:

Compares the contents of data

memory location 'f' to the contents

of WREG by performing an

unsigned subtraction.

If 'f' = WREG

, then the fetched

instruction is discarded and a NOP

is executed instead making this a

two-cycle instruction. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ is 1, the

Bank will be selected as per the BSR

value.

Words:

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

CPFSEQ REG

NEQUAL

EQUAL

Before Instruction

PC Address

HERE

WREG

REG

After Instruction

If REG

WREG;

Address (EQUAL)

If REG

≠

WREG;

Address (NEQUAL)

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